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drivers: added gpio driver for MSPM0 family
Added GPIO driver support for TI MSPM0 family Signed-off-by: Jackson Farley <[email protected]>
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‎drivers/gpio/CMakeLists.txt‎

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@@ -9,6 +9,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_AXP192 gpio_axp192.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_INFINEON_CAT1 gpio_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MSPM0 gpio_mspm0.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_DW gpio_dw.c)

‎drivers/gpio/Kconfig‎

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@@ -121,6 +121,8 @@ source "drivers/gpio/Kconfig.cc13xx_cc26xx"
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source "drivers/gpio/Kconfig.cc32xx"
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source "drivers/gpio/Kconfig.mspm0"
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source "drivers/gpio/Kconfig.sifive"
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source "drivers/gpio/Kconfig.esp32"

‎drivers/gpio/Kconfig.mspm0‎

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# TI MSPM0 GPIO configuration options
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# Copyright (c) 2024 Texas Instruments
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_MSPM0
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bool "TI SimpleLink MSPM0 GPIO driver"
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default y
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depends on DT_HAS_TI_MSPM0_GPIO_ENABLED
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help
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Enable the TI MSPM0 GPIO driver.

‎drivers/gpio/Kconfig.mspm0g3xxx‎

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# TI MSPM0G3XXX GPIO configuration options
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# Copyright (c) 2024 Texas Instruments
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_MSPM0G3XXX
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bool "TI SimpleLink MSPM0G3XXX GPIO driver"
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default y
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depends on DT_HAS_TI_MSPM0G3XXX_GPIO_ENABLED
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help
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Enable the TI MSPM0G3XXX GPIO driver.

‎drivers/gpio/gpio_mspm0.c‎

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/*
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* Copyright (c) 2024 Texas Instruments
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_mspm0_gpio
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/* Zephyr includes */
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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/* Driverlib includes */
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#include <ti/driverlib/dl_gpio.h>
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/* GPIO defines */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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#define GPIOA_NODE DT_NODELABEL(gpioa)
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#ifdef CONFIG_SOC_SERIES_MSPM0G1X0X_G3X0X
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#define NUM_GPIOA_PIN 32
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#define gpioa_pins NUM_GPIOA_PIN
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static uint32_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
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IOMUX_PINCM1, IOMUX_PINCM2, IOMUX_PINCM7, IOMUX_PINCM8, IOMUX_PINCM9,
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IOMUX_PINCM10, IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20,
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IOMUX_PINCM21, IOMUX_PINCM22, IOMUX_PINCM34, IOMUX_PINCM35, IOMUX_PINCM36,
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IOMUX_PINCM37, IOMUX_PINCM38, IOMUX_PINCM39, IOMUX_PINCM40, IOMUX_PINCM41,
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IOMUX_PINCM42, IOMUX_PINCM46, IOMUX_PINCM47, IOMUX_PINCM53, IOMUX_PINCM54,
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IOMUX_PINCM55, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM3, IOMUX_PINCM4,
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IOMUX_PINCM5, IOMUX_PINCM6,
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};
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#else
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#throw "series lookup table not supported"
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#endif /* if config SOC_SERIES_MSPM0G1X0X_G3X0X */
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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#define GPIOB_NODE DT_NODELABEL(gpiob)
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#ifdef CONFIG_SOC_SERIES_MSPM0G1X0X_G3X0X
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#define NUM_GPIOB_PIN 28
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#define gpiob_pins NUM_GPIOB_PIN
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static uint32_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
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IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17,
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IOMUX_PINCM18, IOMUX_PINCM23, IOMUX_PINCM24, IOMUX_PINCM25, IOMUX_PINCM26,
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IOMUX_PINCM27, IOMUX_PINCM28, IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31,
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IOMUX_PINCM32, IOMUX_PINCM33, IOMUX_PINCM43, IOMUX_PINCM44, IOMUX_PINCM45,
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IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51, IOMUX_PINCM52,
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IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM58,
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};
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#endif /* CONFIG_SOC_SERIES */
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */
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struct gpio_mspm0_config {
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/* gpio_mspm0_config needs to be first (doesn't actually get used) */
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struct gpio_driver_config common;
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/* port base address */
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GPIO_Regs *base;
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/* port pincm lookup table */
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uint32_t *pincm_lut;
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};
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struct gpio_mspm0_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t callbacks; /* List of interrupt callbacks */
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};
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static int gpio_mspm0_port_set_bits_raw(const struct device *port, uint32_t mask);
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static int gpio_mspm0_port_clear_bits_raw(const struct device *port, uint32_t mask);
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static int gpio_mspm0_pin_configure(const struct device *port, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* Config pin based on flags */
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switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
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case GPIO_INPUT:
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DL_GPIO_initDigitalInputFeatures(
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config->pincm_lut[pin], DL_GPIO_INVERSION_DISABLE,
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(flags & GPIO_PULL_UP) ? DL_GPIO_RESISTOR_PULL_UP
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: (flags & GPIO_PULL_DOWN) ? DL_GPIO_RESISTOR_PULL_DOWN
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: DL_GPIO_RESISTOR_NONE,
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DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE);
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break;
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case GPIO_OUTPUT:
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DL_GPIO_initDigitalOutputFeatures(config->pincm_lut[pin], DL_GPIO_INVERSION_DISABLE,
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(flags & GPIO_PULL_UP) ? DL_GPIO_RESISTOR_PULL_UP
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: (flags & GPIO_PULL_DOWN)
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? DL_GPIO_RESISTOR_PULL_DOWN
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: DL_GPIO_RESISTOR_NONE,
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DL_GPIO_DRIVE_STRENGTH_LOW, DL_GPIO_HIZ_DISABLE);
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/* Set initial state */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_mspm0_port_set_bits_raw(port, BIT(pin));
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_mspm0_port_clear_bits_raw(port, BIT(pin));
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}
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/* Enable output */
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DL_GPIO_enableOutput(config->base, BIT(pin));
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break;
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case GPIO_DISCONNECTED:
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DL_GPIO_disableOutput(config->base, BIT(pin));
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_mspm0_port_get_raw(const struct device *port, uint32_t *value)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* Read entire port */
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*value = DL_GPIO_readPins(config->base, 0xFFFFFFFF);
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return 0;
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}
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static int gpio_mspm0_port_set_masked_raw(const struct device *port, uint32_t mask,
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uint32_t value)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_writePinsVal(config->base, mask, value);
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return 0;
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}
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static int gpio_mspm0_port_set_bits_raw(const struct device *port, uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_setPins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_port_clear_bits_raw(const struct device *port, uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_clearPins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_port_toggle_bits(const struct device *port, uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_togglePins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* Config interrupt */
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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DL_GPIO_clearInterruptStatus(config->base, BIT(pin));
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DL_GPIO_disableInterrupt(config->base, BIT(pin));
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break;
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case GPIO_INT_MODE_EDGE:
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uint32_t polarity = 0x00;
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if (trig & GPIO_INT_TRIG_LOW) {
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polarity |= 0x01;
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}
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if (trig & GPIO_INT_TRIG_HIGH) {
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polarity |= 0x02;
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}
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if (pin < 16) {
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DL_GPIO_setLowerPinsPolarity(config->base, polarity << (2 * pin));
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} else {
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DL_GPIO_setUpperPinsPolarity(config->base, polarity << (2 * (pin - 16)));
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}
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DL_GPIO_clearInterruptStatus(config->base, BIT(pin));
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DL_GPIO_enableInterrupt(config->base, BIT(pin));
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break;
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case GPIO_INT_MODE_LEVEL:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_mspm0_manage_callback(const struct device *port,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_mspm0_data *data = port->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static uint32_t gpio_mspm0_get_pending_int(const struct device *port)
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{
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const struct gpio_mspm0_config *config = port->config;
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return DL_GPIO_getPendingInterrupt(config->base);
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}
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static void gpio_mspm0_isr(const struct device *port)
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{
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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const struct device *dev_a = DEVICE_DT_GET(GPIOA_NODE);
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struct gpio_mspm0_data *data_a = dev_a->data;
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const struct gpio_mspm0_config *config_a = dev_a->config;
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uint32_t status_a = DL_GPIO_getRawInterruptStatus(config_a->base, 0xFFFFFFFF);
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DL_GPIO_clearInterruptStatus(config_a->base, status_a);
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gpio_fire_callbacks(&data_a->callbacks, dev_a, status_a);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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const struct device *dev_b = DEVICE_DT_GET(GPIOB_NODE);
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struct gpio_mspm0_data *data_b = dev_b->data;
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const struct gpio_mspm0_config *config_b = dev_b->config;
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uint32_t status_b = DL_GPIO_getRawInterruptStatus(config_b->base, 0xFFFFFFFF);
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DL_GPIO_clearInterruptStatus(config_b->base, status_b);
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gpio_fire_callbacks(&data_b->callbacks, dev_b, status_b);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */
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}
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static bool init_irq = true;
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static int gpio_mspm0_init(const struct device *port)
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{
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/* Powering up of GPIOs is part of soc.c */
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if (init_irq) {
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init_irq = false;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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IRQ_CONNECT(DT_IRQN(GPIOB_NODE), DT_IRQ(GPIOB_NODE, priority), gpio_mspm0_isr,
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DEVICE_DT_GET(GPIOB_NODE), 0);
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irq_enable(DT_IRQN(GPIOB_NODE));
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#elif DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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IRQ_CONNECT(DT_IRQN(GPIOA_NODE), DT_IRQ(GPIOA_NODE, priority), gpio_mspm0_isr,
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DEVICE_DT_GET(GPIOA_NODE), 0);
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irq_enable(DT_IRQN(GPIOA_NODE));
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#endif
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}
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return 0;
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}
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#ifdef CONFIG_GPIO_GET_DIRECTION
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static int gpio_mspm0_port_get_direction(const struct device *port, gpio_port_pins_t map,
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gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
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{
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return -ENOTSUP;
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}
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#endif /* CONFIG_GPIO_GET_DIRECTION */
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static const struct gpio_driver_api gpio_mspm0_driver_api = {
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.pin_configure = gpio_mspm0_pin_configure,
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.port_get_raw = gpio_mspm0_port_get_raw,
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.port_set_masked_raw = gpio_mspm0_port_set_masked_raw,
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.port_set_bits_raw = gpio_mspm0_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mspm0_port_clear_bits_raw,
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.port_toggle_bits = gpio_mspm0_port_toggle_bits,
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.pin_interrupt_configure = gpio_mspm0_pin_interrupt_configure,
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.manage_callback = gpio_mspm0_manage_callback,
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.get_pending_int = gpio_mspm0_get_pending_int,
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#ifdef CONFIG_GPIO_GET_DIRECTION
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.port_get_direction = gpio_mspm0_port_get_direction,
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#endif /* CONFIG_GPIO_GET_DIRECTION */
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};
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#define GPIO_DEVICE_INIT(__node, __suffix, __base_addr) \
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static const struct gpio_mspm0_config gpio_mspm0_cfg_##__suffix = { \
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.common = \
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{ \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_NGPIOS(gpio##__suffix##_pins), \
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}, \
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.base = (GPIO_Regs *)__base_addr, \
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.pincm_lut = gpio##__suffix##_pincm_lut, \
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}; \
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static struct gpio_mspm0_data gpio_mspm0_data_##__suffix; \
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DEVICE_DT_DEFINE(__node, gpio_mspm0_init, NULL, &gpio_mspm0_data_##__suffix, \
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&gpio_mspm0_cfg_##__suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_mspm0_driver_api)
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#define GPIO_DEVICE_INIT_MSPM0(__suffix) \
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GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), __suffix, \
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DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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GPIO_DEVICE_INIT_MSPM0(a);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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GPIO_DEVICE_INIT_MSPM0(b);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */

‎dts/bindings/gpio/ti,mspm0-gpio.yaml‎

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# SPDX-License-Identifier: Apache-2.0
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description: TI MSPM0 GPIO
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compatible: "ti,mspm0-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

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