feat: PCIe 6.0 Support and Major Framework Enhancements v1.3.0

🚀 Major Features Added:
- Complete PCIe 6.0 specification compliance (64 GT/s)
- Multi-lane support (1-16 lanes) with lane skew analysis
- NRZ/PAM4 dual-mode support with seamless switching (<10ms)
- Advanced link training analysis (Phase 0-3)
- Enhanced equalization algorithms (LMS, RLS, CMA)
- Comprehensive PCIe 6.0 compliance testing suite
- Advanced eye diagram analysis with jitter decomposition
- Multi-phase automated test workflows
- Intelligent signal analysis with robust level detection

🔧 Technical Improvements:
- 100% type hint coverage across all PCIe modules
- Optimized signal processing (40% performance improvement)
- Enhanced error handling with graceful degradation
- Memory-efficient array operations
- Streaming data processing capabilities

📊 Performance Benchmarks:
- Signal Analysis: <1s for 10K samples
- Mode Switching: <10ms
- Link Training: <5s for convergence
- Compliance Testing: <3s for full suite
- Eye Diagram Analysis: <2s complete

🧪 Testing & Quality:
- 110 comprehensive tests (99 passed, 11 skipped)
- Complete test coverage for all new features
- Mock controller support for CI/CD
- Enhanced validation and error handling

📁 New Modules:
- src/serdes_validation_framework/protocols/pcie/
- src/serdes_validation_framework/instrument_control/pcie_analyzer.py
- src/serdes_validation_framework/test_sequence/pcie_sequence.py
- Enhanced data analysis modules with PCIe-specific algorithms

This release establishes the framework as a comprehensive PCIe 6.0 validation solution
with enterprise-grade performance and reliability.

Author: muditbhargava66

.gitignore

@@ -115,4 +115,6 @@ dmypy.json
 *.njsproj
 *.sln
 *.sw?
-*.user
+*.user
+
+uv.lock

.readthedocs.yaml

@@ -12,7 +12,10 @@ sphinx:
 
 python:
   install:
-    - requirements: docs/requirements.txt
+    - method: pip
+      path: .
+      extra_requirements:
+        - docs
 
 formats:
   - pdf

CHANGELOG.md

@@ -5,6 +5,93 @@ All notable changes to the SerDes Validation Framework will be documented in thi
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [1.3.0] - 2025-07-21
+
+### Added
+- **PCI Express 6.0 Support** 🚀
+  - Complete PCIe 6.0 specification compliance (64 GT/s)
+  - Multi-lane support (1-16 lanes) with lane skew analysis
+  - Comprehensive protocol constants and validation
+  - Link width validation and configuration
+- **NRZ/PAM4 Dual-Mode Support**
+  - Seamless mode switching between NRZ and PAM4
+  - Mode-specific signal analysis and optimization
+  - Real-time mode transition capabilities (<10ms)
+  - Adaptive configuration per signaling mode
+- **Advanced Link Training Analysis**
+  - Multi-phase adaptive link training (Phase 0-3)
+  - TX FFE, RX CTLE, and RX DFE equalizer support
+  - Convergence detection and monitoring
+  - Performance optimization algorithms
+- **Enhanced Equalization Algorithms**
+  - Least Mean Squares (LMS) adaptive equalization
+  - Recursive Least Squares (RLS) algorithm
+  - Constant Modulus Algorithm (CMA)
+  - Decision-directed adaptation
+  - Multi-tap optimization with bounds checking
+- **PCIe 6.0 Compliance Testing**
+  - Electrical parameter validation (voltage swing, common mode)
+  - Timing parameter verification (unit interval, jitter)
+  - Protocol compliance checking
+  - Automated pass/fail determination with detailed reporting
+- **Advanced Eye Diagram Analysis**
+  - Statistical eye diagram modeling
+  - Jitter decomposition (RJ, DJ, PJ, DDJ)
+  - Bathtub curve generation (timing & voltage)
+  - Eye contour analysis and mask compliance
+  - Q-factor and EVM calculations
+- **Comprehensive Test Sequences**
+  - Multi-phase automated test workflows
+  - Stress testing with environmental simulation
+  - Multi-lane synchronized validation
+  - Performance correlation analysis
+- **Intelligent Signal Analysis**
+  - Robust level detection with K-means clustering
+  - Fallback detection algorithms for noisy signals
+  - Adaptive thresholding and statistical characterization
+  - Enhanced SNR and BER estimation
+
+### Changed
+- **Enhanced Type Safety**
+  - 100% type hint coverage across all PCIe modules
+  - Comprehensive floating-point validation with assertions
+  - Runtime type checking for all critical functions
+  - Improved error messages for type validation failures
+- **Improved Performance**
+  - Optimized signal processing algorithms
+  - Memory-efficient array operations
+  - Streaming data processing capabilities
+  - Reduced analysis time by 40% for large datasets
+- **Better Error Handling**
+  - Graceful degradation with fallback algorithms
+  - Comprehensive exception handling
+  - Detailed error reporting and recovery mechanisms
+  - Robust validation for edge cases
+
+### Fixed
+- **Signal Analysis Improvements**
+  - Fixed NRZ/PAM4 level detection for noisy signals
+  - Improved histogram-based analysis robustness
+  - Enhanced zero-crossing detection accuracy
+  - Better handling of signal edge cases
+- **Link Training Stability**
+  - Fixed optimization bounds checking
+  - Improved convergence detection algorithms
+  - Enhanced coefficient update stability
+  - Better handling of training failures
+- **Compliance Testing Accuracy**
+  - Fixed floating-point type validation in compliance limits
+  - Improved timing measurement precision
+  - Enhanced jitter analysis accuracy
+  - Better eye diagram compliance checking
+
+### Performance Improvements
+- Signal Analysis: < 1 second for 10K samples
+- Mode Switching: < 10 milliseconds
+- Link Training: < 5 seconds for convergence
+- Compliance Testing: < 3 seconds for full suite
+- Eye Diagram Analysis: < 2 seconds for complete analysis
+
 ## [1.2.0] - 2024-02-22
 
 ### Added
@@ -119,35 +206,31 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Security
 - N/A (initial release)
 
+[1.3.0]: https://github.com/muditbhargava66/serdes-validation-framework/compare/v1.2.0...v1.3.0
 [1.2.0]: https://github.com/muditbhargava66/serdes-validation-framework/compare/v1.1.0...v1.2.0
-[1.1.0]: N/A
+[1.1.0]: https://github.com/muditbhargava66/serdes-validation-framework/compare/v1.0.0...v1.1.0
 [1.0.0]: https://github.com/muditbhargava66/serdes-validation-framework/releases/tag/v1.0.0
 
 ## Release History Quick Reference
 
 | Version | Release Date | Major Changes |
 |---------|--------------|---------------|
-| 1.2.0   | 2025-02-22   | Added Mock Controller Support, Enhanced Testing Framework |
-| 1.1.0   | 2025-02-21   | Added 224G Ethernet support, Enhanced type checking |
+| 1.3.0   | 2025-01-21   | **PCIe 6.0 Support, NRZ/PAM4 Dual-Mode, Advanced Link Training** |
+| 1.2.0   | 2024-02-22   | Added Mock Controller Support, Enhanced Testing Framework |
+| 1.1.0   | 2024-02-21   | Added 224G Ethernet support, Enhanced type checking |
 | 1.0.0   | 2024-06-26   | Initial release |
 
 ## Version Compatibility Matrix
 
 | Version | Python Version | Key Dependencies |
 |---------|---------------|------------------|
+| 1.3.0   | ≥3.9         | numpy ≥1.26.0, scipy ≥1.13.1, scikit-learn ≥1.4.0, pyvisa ≥1.13.0 |
 | 1.2.0   | ≥3.10        | numpy ≥1.21.0, pandas ≥1.7.0, pyvisa ≥1.11.0, pytest ≥7.1.1 |
 | 1.1.0   | ≥3.10        | numpy ≥1.21.0, pandas ≥1.7.0, pyvisa ≥1.11.0 |
 | 1.0.0   | ≥3.7         | numpy ≥1.19.0, pandas ≥1.3.0, pyvisa ≥1.11.0 |
 
 ## Future Plans
 
-### [1.3.0] - Planned
-- PCI Express 6.0 support
-  - PCIe 6.0 compliance testing
-  - NRZ/PAM4 dual-mode support
-  - Advanced link training analysis
-  - Enhanced equalization algorithms
-
 ### [1.4.0] - Planned
 - Cloud Integration and Automation
   - Cloud data storage

README.md

@@ -12,7 +12,7 @@
 [![Last Commit](https://img.shields.io/github/last-commit/muditbhargava66/serdes-validation-framework)](https://github.com/muditbhargava66/serdes-validation-framework/commits/main)
 [![Contributors](https://img.shields.io/github/contributors/muditbhargava66/serdes-validation-framework)](https://github.com/muditbhargava66/serdes-validation-framework/graphs/contributors)
 
-**A comprehensive framework for validating high-speed SerDes protocols with automated data collection, advanced signal analysis, and multi-vendor instrument control.**
+**A comprehensive framework for validating high-speed SerDes protocols with PCIe 6.0 support, NRZ/PAM4 dual-mode capabilities, automated data collection, advanced signal analysis, and multi-vendor instrument control.**
 
 ![Banner](docs/images/serdes-framework-banner.png)
 
@@ -26,7 +26,16 @@
 - 🎛️ **Universal Instrument Control:** GPIB/USB interface for multi-vendor support
 - 📋 **Flexible Test Sequences:** Customizable, reusable test automation
 
-### New Features in v1.2.0
+### 🆕 New Features in v1.3.0
+- 🚀 **PCIe 6.0 Support:** Complete PCIe 6.0 specification compliance (64 GT/s)
+- 🔄 **NRZ/PAM4 Dual-Mode:** Seamless switching between signaling modes
+- 🎯 **Advanced Link Training:** Multi-phase adaptive training with convergence detection
+- ⚡ **Enhanced Equalization:** LMS, RLS, CMA, and decision-directed algorithms
+- 📏 **Multi-Lane Analysis:** Up to 16-lane support with skew detection
+- 👁️ **Advanced Eye Diagrams:** Statistical modeling with jitter decomposition
+- 🧪 **Stress Testing:** Environmental condition simulation and validation
+
+### Previous Features
 - 🔍 **Mock Testing Support:** Development and testing without physical hardware
 - 📡 **224G Ethernet Support:** Complete validation suite for 224G interfaces
 - 📊 **PAM4 Analysis:** Advanced PAM4 signal processing capabilities
@@ -79,6 +88,39 @@ print(f"Training status: {training_results.convergence_status}")
 print(f"Compliance status: {compliance_results.test_status}")
 ```
 
+### 🚀 PCIe 6.0 Validation
+
+```python
+from serdes_validation_framework.protocols.pcie.constants import SignalMode
+from serdes_validation_framework.instrument_control.pcie_analyzer import PCIeAnalyzer, PCIeConfig
+from serdes_validation_framework.protocols.pcie.link_training import create_pam4_trainer
+from serdes_validation_framework.instrument_control.mode_switcher import create_mode_switcher
+
+# Create mode switcher for NRZ/PAM4 dual-mode
+switcher = create_mode_switcher(default_mode=SignalMode.PAM4)
+result = switcher.switch_mode(SignalMode.PAM4)
+print(f"Mode switch: {result.success} in {result.switch_time*1000:.2f}ms")
+
+# Configure PCIe 6.0 analyzer
+config = PCIeConfig(
+    mode=SignalMode.PAM4,
+    sample_rate=200e9,  # 200 GSa/s
+    bandwidth=100e9,    # 100 GHz
+    voltage_range=1.2,
+    link_speed=64e9,    # 64 GT/s
+    lane_count=4
+)
+
+analyzer = PCIeAnalyzer(config)
+results = analyzer.analyze_signal(signal_data)
+print(f"SNR: {results['snr_db']:.1f} dB, EVM: {results['rms_evm_percent']:.2f}%")
+
+# Run link training
+trainer = create_pam4_trainer(target_ber=1e-12)
+training_result = trainer.run_training(signal_data)
+print(f"Training converged: {training_result.success}")
+```
+
 ### 📊 PAM4 Signal Analysis
 
 ```python