@@ -1652,7 +1652,7 @@ TEST_F(CompilerPipelineTest, MCXTrivial) {
16521652}
16531653
16541654TEST_F (CompilerPipelineTest, InvX) {
1655- auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
1655+ const auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
16561656 auto reg = b.allocQubitRegister (1 , " q" );
16571657 b.inv ([&] { b.x (reg[0 ]); });
16581658 });
@@ -1686,7 +1686,7 @@ TEST_F(CompilerPipelineTest, InvX) {
16861686}
16871687
16881688TEST_F (CompilerPipelineTest, InvRx) {
1689- auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
1689+ const auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
16901690 auto reg = b.allocQubitRegister (1 , " q" );
16911691 b.inv ([&] { b.rx (0.5 , reg[0 ]); });
16921692 });
@@ -1720,7 +1720,7 @@ TEST_F(CompilerPipelineTest, InvRx) {
17201720}
17211721
17221722TEST_F (CompilerPipelineTest, NestedInvs) {
1723- auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
1723+ const auto input = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
17241724 auto reg = b.allocQubitRegister (2 , " q" );
17251725 b.inv ([&] { b.inv ([&] { b.iswap (reg[0 ], reg[1 ]); }); });
17261726 });
@@ -1757,19 +1757,17 @@ TEST_F(CompilerPipelineTest, NestedInvCtrlS) {
17571757
17581758 ASSERT_TRUE (runPipeline (input.get ()).succeeded ());
17591759
1760- auto qcInit = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
1760+ const auto qcInit = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
17611761 auto reg = b.allocQubitRegister (2 , " q" );
17621762 b.ctrl (reg[0 ], [&] { b.inv ([&] { b.s (reg[1 ]); }); });
17631763 });
17641764 const auto qco = buildQCOIR ([](qco::QCOProgramBuilder& b) {
17651765 auto reg = b.allocQubitRegister (2 , " q" );
1766- b.ctrl (reg[0 ], reg[1 ], [&](auto targets) -> llvm::SmallVector<Value> {
1767- return {b.sdg (targets[0 ])};
1768- });
1766+ b.csdg (reg[0 ], reg[1 ]);
17691767 });
17701768 const auto qc = buildQCIR ([](mlir::qc::QCProgramBuilder& b) {
17711769 auto reg = b.allocQubitRegister (2 , " q" );
1772- b.ctrl (reg[0 ], [&] { b. sdg ( reg[1 ]); } );
1770+ b.csdg (reg[0 ], reg[1 ]);
17731771 });
17741772 const auto qir = buildQIR ([](qir::QIRProgramBuilder& b) {
17751773 auto reg = b.allocQubitRegister (2 );
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