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Commit 9596180

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Gillou68310
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new_dynarec: Fix regression on arm64 caused by 26cc980 
1 parent ca1888d commit 9596180

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3 files changed

+51
-59
lines changed

3 files changed

+51
-59
lines changed

‎src/device/r4300/new_dynarec/arm/assem_arm.c‎

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2245,6 +2245,12 @@ static void emit_addsr12(int rs1,int rs2,int rt)
22452245
output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
22462246
}
22472247

2248+
static void emit_addsl2(int rs1,int rs2,int rt)
2249+
{
2250+
assem_debug("add %s,%s,%s lsl #2",regname[rt],regname[rs1],regname[rs2]);
2251+
output_w32(0xe0800100|rd_rn_rm(rt,rs1,rs2));
2252+
}
2253+
22482254
static void emit_callne(int a)
22492255
{
22502256
assem_debug("blne %x",a);
@@ -3066,21 +3072,6 @@ static void do_tlb_w_branch_debug(int map, int c, u_int addr, int *jaddr)
30663072
}
30673073
}
30683074

3069-
static void gen_addr(int ar, int map) {
3070-
if(map>=0) {
3071-
assem_debug("add %s,%s,%s lsl #2",regname[ar],regname[ar],regname[map]);
3072-
output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3073-
}
3074-
}
3075-
3076-
// This reverses the above operation
3077-
static void gen_orig_addr(int ar, int map) {
3078-
if(map>=0) {
3079-
assem_debug("sub %s,%s,%s lsl #2",regname[ar],regname[ar],regname[map]);
3080-
output_w32(0xe0400100|rd_rn_rm(ar,ar,map));
3081-
}
3082-
}
3083-
30843075
// Generate the address of the memory_map entry, relative to dynarec_local
30853076
static void generate_map_const(u_int addr,int reg) {
30863077
//DebugMessage(M64MSG_VERBOSE, "generate_map_const(%x,%s)",addr,regname[reg]);

‎src/device/r4300/new_dynarec/arm64/assem_arm64.c‎

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2498,6 +2498,12 @@ static void emit_addsr12(int rs1,int rs2,int rt)
24982498
output_w32(0x0b400000|rs2<<16|12<<10|rs1<<5|rt);
24992499
}
25002500

2501+
static void emit_addsl2(int rs1,int rs2,int rt)
2502+
{
2503+
assem_debug("add %s,%s,%s lsl #2",regname64[rt],regname64[rs1],regname64[rs2]);
2504+
output_w32(0x8b000000|rs2<<16|2<<10|rs1<<5|rt);
2505+
}
2506+
25012507
#ifdef HAVE_CONDITIONAL_CALL
25022508
static void emit_callne(intptr_t a)
25032509
{
@@ -3585,21 +3591,6 @@ static void do_tlb_w_branch_debug(int map, int c, u_int addr, intptr_t *jaddr)
35853591
}
35863592
}
35873593

3588-
static void gen_addr(int ar, int map) {
3589-
if(map>=0) {
3590-
assem_debug("add %s,%s,%s lsl #2",regname64[ar],regname64[ar],regname64[map]);
3591-
output_w32(0x8b000000|map<<16|2<<10|ar<<5|ar);
3592-
}
3593-
}
3594-
3595-
// This reverses the above operation
3596-
static void gen_orig_addr(int ar, int map) {
3597-
if(map>=0) {
3598-
assem_debug("sub %s,%s,%s lsl #2",regname64[ar],regname64[ar],regname64[map]);
3599-
output_w32(0xcb000000|map<<16|2<<10|ar<<5|ar);
3600-
}
3601-
}
3602-
36033594
// Generate the address of the memory_map entry, relative to dynarec_local
36043595
static void generate_map_const(u_int addr,int tr) {
36053596
//DebugMessage(M64MSG_VERBOSE, "generate_map_const(%x,%s)",addr,regname[tr]);

‎src/device/r4300/new_dynarec/new_dynarec.c‎

Lines changed: 39 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -4222,7 +4222,7 @@ static void store_assemble(int i,struct regstat *i_regs)
42224222
static void storelr_assemble(int i,struct regstat *i_regs)
42234223
{
42244224
int s,th,tl;
4225-
int temp;
4225+
int temp,real_temp;
42264226
int temp2;
42274227
int map=-1;
42284228
int offset;
@@ -4279,34 +4279,37 @@ static void storelr_assemble(int i,struct regstat *i_regs)
42794279
emit_jmp(0);
42804280
}
42814281
}
4282+
real_temp=temp;
42824283
#if NEW_DYNAREC >= NEW_DYNAREC_ARM
4283-
gen_addr(temp,map);
4284-
map=-1;
4284+
if(map>=0){
4285+
emit_addsl2(real_temp,map,map);
4286+
temp=map; map=-1;
4287+
}
42854288
#endif
42864289

42874290
if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
42884291
temp2=get_reg(i_regs->regmap,FTEMP);
42894292
if(!rs2[i]) temp2=th=tl;
42904293
}
42914294

4292-
emit_testimm(temp,2);
4295+
emit_testimm(real_temp,2);
42934296
case2=(intptr_t)out;
42944297
emit_jne(0);
4295-
emit_testimm(temp,1);
4298+
emit_testimm(real_temp,1);
42964299
case1=(intptr_t)out;
42974300
emit_jne(0);
42984301
// 0
42994302
if (opcode[i]==0x2A) { // SWL
43004303
emit_writeword_indexed_tlb(tl,0,temp,map);
43014304
}
4302-
if (opcode[i]==0x2E) { // SWR
4305+
else if (opcode[i]==0x2E) { // SWR
43034306
emit_writebyte_indexed_tlb(tl,3,temp,map);
43044307
}
4305-
if (opcode[i]==0x2C) { // SDL
4308+
else if (opcode[i]==0x2C) { // SDL
43064309
emit_writeword_indexed_tlb(th,0,temp,map);
43074310
if(rs2[i]) emit_mov(tl,temp2);
43084311
}
4309-
if (opcode[i]==0x2D) { // SDR
4312+
else if (opcode[i]==0x2D) { // SDR
43104313
emit_writebyte_indexed_tlb(tl,3,temp,map);
43114314
if(rs2[i]) emit_shldimm(th,tl,24,temp2);
43124315
}
@@ -4322,11 +4325,11 @@ static void storelr_assemble(int i,struct regstat *i_regs)
43224325
emit_writebyte_indexed_tlb(tl,1,temp,map);
43234326
if(rs2[i]) emit_rorimm(tl,8,tl);
43244327
}
4325-
if (opcode[i]==0x2E) { // SWR
4328+
else if (opcode[i]==0x2E) { // SWR
43264329
// Write two lsb into two most significant bytes
43274330
emit_writehword_indexed_tlb(tl,1,temp,map);
43284331
}
4329-
if (opcode[i]==0x2C) { // SDL
4332+
else if (opcode[i]==0x2C) { // SDL
43304333
if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
43314334
// Write 3 msb into three least significant bytes
43324335
if(rs2[i]) emit_rorimm(th,8,th);
@@ -4335,7 +4338,7 @@ static void storelr_assemble(int i,struct regstat *i_regs)
43354338
emit_writebyte_indexed_tlb(th,1,temp,map);
43364339
if(rs2[i]) emit_rorimm(th,8,th);
43374340
}
4338-
if (opcode[i]==0x2D) { // SDR
4341+
else if (opcode[i]==0x2D) { // SDR
43394342
if(rs2[i]) emit_shldimm(th,tl,16,temp2);
43404343
// Write two lsb into two most significant bytes
43414344
emit_writehword_indexed_tlb(tl,1,temp,map);
@@ -4344,7 +4347,7 @@ static void storelr_assemble(int i,struct regstat *i_regs)
43444347
emit_jmp(0);
43454348
// 2
43464349
set_jump_target(case2,(intptr_t)out);
4347-
emit_testimm(temp,1);
4350+
emit_testimm(real_temp,1);
43484351
case3=(intptr_t)out;
43494352
emit_jne(0);
43504353
if (opcode[i]==0x2A) { // SWL
@@ -4353,21 +4356,21 @@ static void storelr_assemble(int i,struct regstat *i_regs)
43534356
emit_writehword_indexed_tlb(tl,-2,temp,map);
43544357
if(rs2[i]) emit_rorimm(tl,16,tl);
43554358
}
4356-
if (opcode[i]==0x2E) { // SWR
4359+
else if (opcode[i]==0x2E) { // SWR
43574360
// Write 3 lsb into three most significant bytes
43584361
emit_writebyte_indexed_tlb(tl,-1,temp,map);
43594362
if(rs2[i]) emit_rorimm(tl,8,tl);
43604363
emit_writehword_indexed_tlb(tl,0,temp,map);
43614364
if(rs2[i]) emit_rorimm(tl,24,tl);
43624365
}
4363-
if (opcode[i]==0x2C) { // SDL
4366+
else if (opcode[i]==0x2C) { // SDL
43644367
if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
43654368
// Write two msb into two least significant bytes
43664369
if(rs2[i]) emit_rorimm(th,16,th);
43674370
emit_writehword_indexed_tlb(th,-2,temp,map);
43684371
if(rs2[i]) emit_rorimm(th,16,th);
43694372
}
4370-
if (opcode[i]==0x2D) { // SDR
4373+
else if (opcode[i]==0x2D) { // SDR
43714374
if(rs2[i]) emit_shldimm(th,tl,8,temp2);
43724375
// Write 3 lsb into three most significant bytes
43734376
emit_writebyte_indexed_tlb(tl,-1,temp,map);
@@ -4385,18 +4388,18 @@ static void storelr_assemble(int i,struct regstat *i_regs)
43854388
emit_writebyte_indexed_tlb(tl,-3,temp,map);
43864389
if(rs2[i]) emit_rorimm(tl,8,tl);
43874390
}
4388-
if (opcode[i]==0x2E) { // SWR
4391+
else if (opcode[i]==0x2E) { // SWR
43894392
// Write entire word
43904393
emit_writeword_indexed_tlb(tl,-3,temp,map);
43914394
}
4392-
if (opcode[i]==0x2C) { // SDL
4395+
else if (opcode[i]==0x2C) { // SDL
43934396
if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
43944397
// Write msb into least significant byte
43954398
if(rs2[i]) emit_rorimm(th,24,th);
43964399
emit_writebyte_indexed_tlb(th,-3,temp,map);
43974400
if(rs2[i]) emit_rorimm(th,8,th);
43984401
}
4399-
if (opcode[i]==0x2D) { // SDR
4402+
else if (opcode[i]==0x2D) { // SDR
44004403
if(rs2[i]) emit_mov(th,temp2);
44014404
// Write entire word
44024405
emit_writeword_indexed_tlb(tl,-3,temp,map);
@@ -4405,44 +4408,51 @@ static void storelr_assemble(int i,struct regstat *i_regs)
44054408
set_jump_target(done1,(intptr_t)out);
44064409
set_jump_target(done2,(intptr_t)out);
44074410
if (opcode[i]==0x2C) { // SDL
4408-
emit_testimm(temp,4);
4411+
emit_testimm(real_temp,4);
44094412
done0=(intptr_t)out;
44104413
emit_jne(0);
4414+
#if NEW_DYNAREC == NEW_DYNAREC_ARM64
4415+
emit_andimm64(temp,~3,temp);
4416+
#else
44114417
emit_andimm(temp,~3,temp);
4418+
#endif
44124419
emit_writeword_indexed_tlb(temp2,4,temp,map);
44134420
set_jump_target(done0,(intptr_t)out);
44144421
}
4415-
if (opcode[i]==0x2D) { // SDR
4416-
emit_testimm(temp,4);
4422+
else if (opcode[i]==0x2D) { // SDR
4423+
emit_testimm(real_temp,4);
44174424
done0=(intptr_t)out;
44184425
emit_jeq(0);
4426+
#if NEW_DYNAREC == NEW_DYNAREC_ARM64
4427+
emit_andimm64(temp,~3,temp);
4428+
#else
44194429
emit_andimm(temp,~3,temp);
4430+
#endif
44204431
emit_writeword_indexed_tlb(temp2,-4,temp,map);
44214432
set_jump_target(done0,(intptr_t)out);
44224433
}
4423-
if(!c||!memtarget)
4424-
add_stub(STORELR_STUB,jaddr,(intptr_t)out,0,(intptr_t)i_regs,rs2[i],ccadj[i],reglist);
44254434
if(!using_tlb) {
44264435
#if NEW_DYNAREC >= NEW_DYNAREC_ARM
44274436
map=get_reg(i_regs->regmap,ROREG);
4428-
if(map<0) map=HOST_TEMPREG;
4429-
gen_orig_addr(temp,map);
4437+
if(map>=0) emit_loadreg(ROREG,map);
44304438
#endif
44314439
#if defined(HOST_IMM8) || defined(NEED_INVC_PTR)
44324440
int ir=get_reg(i_regs->regmap,INVCP);
44334441
assert(ir>=0);
4434-
emit_cmpmem_indexedsr12_reg(ir,temp,1);
4442+
emit_cmpmem_indexedsr12_reg(ir,real_temp,1);
44354443
#else
4436-
emit_cmpmem_indexedsr12_imm((intptr_t)g_dev.r4300.cached_interp.invalid_code,temp,1);
4444+
emit_cmpmem_indexedsr12_imm((intptr_t)g_dev.r4300.cached_interp.invalid_code,real_temp,1);
44374445
#endif
44384446
#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
4439-
emit_callne(invalidate_addr_reg[temp]);
4447+
emit_callne(invalidate_addr_reg[real_temp]);
44404448
#else
44414449
intptr_t jaddr2=(intptr_t)out;
44424450
emit_jne(0);
4443-
add_stub(INVCODE_STUB,jaddr2,(intptr_t)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
4451+
add_stub(INVCODE_STUB,jaddr2,(intptr_t)out,reglist|(1<<HOST_CCREG),real_temp,0,0,0);
44444452
#endif
44454453
}
4454+
if(!c||!memtarget)
4455+
add_stub(STORELR_STUB,jaddr,(intptr_t)out,0,(intptr_t)i_regs,rs2[i],ccadj[i],reglist);
44464456
}
44474457
#endif
44484458

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