@@ -65,9 +65,9 @@ static void do_sp_dma(struct rsp_core* sp, const struct sp_dma* dma)
6565 dramaddr += skip ;
6666 }
6767
68- sp -> regs [SP_MEM_ADDR_REG ] = memaddr & 0xfff ;
69- sp -> regs [SP_DRAM_ADDR_REG ] = dramaddr & 0xffffff ;
70- sp -> regs [SP_RD_LEN_REG ] = 0xff8 ;
68+ sp -> regs [SP_MEM_ADDR_REG ] = memaddr & 0xfff ;
69+ sp -> regs [SP_DRAM_ADDR_REG ] = dramaddr & 0xffffff ;
70+ sp -> regs [SP_RD_LEN_REG ] = 0xff8 ;
7171 }
7272 else
7373 {
@@ -82,9 +82,9 @@ static void do_sp_dma(struct rsp_core* sp, const struct sp_dma* dma)
8282 dramaddr += skip ;
8383 }
8484
85- sp -> regs [SP_MEM_ADDR_REG ] = memaddr & 0xfff ;
86- sp -> regs [SP_DRAM_ADDR_REG ] = dramaddr & 0xffffff ;
87- sp -> regs [SP_RD_LEN_REG ] = 0xff8 ;
85+ sp -> regs [SP_MEM_ADDR_REG ] = memaddr & 0xfff ;
86+ sp -> regs [SP_DRAM_ADDR_REG ] = dramaddr & 0xffffff ;
87+ sp -> regs [SP_RD_LEN_REG ] = 0xff8 ;
8888 }
8989
9090 /* schedule end of dma event */
@@ -172,7 +172,7 @@ static void update_sp_status(struct rsp_core* sp, uint32_t w)
172172
173173 /* clear / set signal 0 */
174174 if ((w & 0x600 ) == 0x200 ) sp -> regs [SP_STATUS_REG ] &= ~SP_STATUS_SIG0 ;
175- if ((w & 0x600 ) == 0x400 )
175+ if ((w & 0x600 ) == 0x400 ) sp -> regs [ SP_STATUS_REG ] |= SP_STATUS_SIG0 ;
176176
177177 /* clear / set signal 1 */
178178 if ((w & 0x1800 ) == 0x800 ) sp -> regs [SP_STATUS_REG ] &= ~SP_STATUS_SIG1 ;
@@ -276,7 +276,6 @@ void write_rsp_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mas
276276 {
277277 case SP_STATUS_REG :
278278 update_sp_status (sp , value & mask );
279- return ;
280279 case SP_DMA_FULL_REG :
281280 case SP_DMA_BUSY_REG :
282281 return ;
@@ -319,7 +318,6 @@ void write_rsp_regs2(void* opaque, uint32_t address, uint32_t value, uint32_t ma
319318 if (reg == SP_PC_REG )
320319 mask &= 0xffc ;
321320
322-
323321 masked_write (& sp -> regs2 [reg ], value , mask );
324322}
325323
0 commit comments