source formatting

Author: rjonaitis

.clang-format

@@ -105,7 +105,7 @@ SpacesInCStyleCastParentheses: false
 SpacesInParentheses: false
 SpacesInSquareBrackets: false
 Standard:        Cpp11
-TabWidth:        8
+TabWidth:        4
 UseTab:          Never
 ...
 

Sources/iqmod_rx.c

@@ -245,7 +245,7 @@ void RX_IQ_DATA_TO_DDR(void) {
     return;
 }
 
-//#pragma optimize_for_size off
+// #pragma optimize_for_size off
 volatile uint32_t rx_busy_size = 0;
 void PUSH_RX_DATA(void) {
     uint32_t tmp_status;

Sources/iqmod_rx_2R_decx2x4.c

@@ -229,7 +229,7 @@ void RX_IQ_DATA_TO_DDR(void) {
     return;
 }
 
-//#pragma optimize_for_size off
+// #pragma optimize_for_size off
 volatile uint32_t rx_busy_size = 0;
 void PUSH_RX_DATA(void) {
     uint32_t tmp_status, i;

Sources/iqmod_tx.c

@@ -278,7 +278,7 @@ void TX_IQ_DATA_FROM_DDR(void) {
     return;
 }
 
-//#pragma optimize_for_size off
+// #pragma optimize_for_size off
 volatile uint32_t tx_busy_size = 0;
 void PUSH_TX_DATA(void) {
     uint32_t tmp_status;

Sources/iqmod_tx_2R.c

@@ -251,7 +251,7 @@ void TX_IQ_DATA_FROM_DDR(void) {
     return;
 }
 
-//#pragma optimize_for_size off
+// #pragma optimize_for_size off
 volatile uint32_t tx_busy_size = 0;
 void PUSH_TX_DATA(void) {
     uint32_t tmp_status;

include/dfe.h

@@ -19,8 +19,8 @@
  *   txiqcomp			 IQ phase and amplitude compensation
  *   txiqcomp_x32chf_5t  IQ phase and amplitude + IQ fractional delay compensation
  */
-//#define TXIQCOMP2
-//#define RXIQCOMP2
+// #define TXIQCOMP2
+// #define RXIQCOMP2
 #define TXIQCOMP
 #define RXIQCOMP
 

include/iqmod_tx.h

@@ -59,8 +59,8 @@ extern uint32_t tx_proxy_updated;
 #define DDR_RD_DMA_CHANNEL_2 0x8
 #define DDR_RD_DMA_CHANNEL_3 0x9
 #define DDR_RD_DMA_CHANNEL_4 0xa
-//#define DDR_RD_DMA_CHANNEL_MASK 0x00000180
-//#define DDR_RD_DMA_CHANNEL_MASK 0x00000780
+// #define DDR_RD_DMA_CHANNEL_MASK 0x00000180
+// #define DDR_RD_DMA_CHANNEL_MASK 0x00000780
 
 #define DMA_CHANNEL_WR 0xb
 

include/main.h

@@ -16,8 +16,8 @@
 #include "iohw.h"
 #include "dmac.h"
 #include "axiq.h"
-//#include "bitRev.h"
-//#include "la9310.h"
+// #include "bitRev.h"
+// #include "la9310.h"
 
 /* parameters */
 
@@ -94,7 +94,7 @@ typedef enum {
     MBOX_OPC_GET_STATS_COUNT, // 0xF
     MBOX_OPC_DONE_SWRESET,    // 0x10
     MBOX_OPC_PROXY_OFFSET     // 0x11
-   
+
 } mbox_opc_e;
 
 void PUSH_TX_DATA(void);

vspa-sdk/inc/axiq-hs.h

@@ -35,7 +35,7 @@ enum axiq_hs_fifo_e {
 #define AXIQ_HS_CR_TX_SHIFT 16
 
 //! @brief      Number of right-shifts to right-justify the FIFO control bits.
-#define AXIQ_HS_CR_SHIFT(bank, fifo) ((fifo)*16)
+#define AXIQ_HS_CR_SHIFT(bank, fifo) ((fifo) * 16)
 
 #define AXIQ_HS_CR_SHIFT_RX(bank, fifo) AXIQ_HS_CR_SHIFT(bank, fifo)
 #define AXIQ_HS_CR_SHIFT_TX(bank, fifo) AXIQ_HS_CR_SHIFT(bank, fifo)
@@ -90,7 +90,7 @@ enum axiq_hs_fifo_e {
 // Status register:
 // =============================================================================
 
-#define AXIQ_HS_SR_SHIFT(bank, fifo) (((bank)*16) + ((fifo)*8))
+#define AXIQ_HS_SR_SHIFT(bank, fifo) (((bank) * 16) + ((fifo) * 8))
 
 #define AXIQ_HS_SR_SHIFT_RX(bank, fifo) AXIQ_HS_SR_SHIFT(bank, AXIQ_HS_FIFO_RX)
 #define AXIQ_HS_SR_SHIFT_TX(bank, fifo) AXIQ_HS_SR_SHIFT(bank, AXIQ_HS_FIFO_TX)

vspa-sdk/inc/axiq-la1224.h

@@ -57,26 +57,26 @@ enum axiq_ls_bank_e {
 // -----------------------------------------------------------------------------
 
 //! @brief      AXIQ RX control register address.
-#define AXIQ_LS_RX_CR(bank) GPO(((bank)*2) + GPIO_AXIQ_L0_CR0)
+#define AXIQ_LS_RX_CR(bank) GPO(((bank) * 2) + GPIO_AXIQ_L0_CR0)
 
 //! @brief      AXIQ TX control register address.
-#define AXIQ_LS_TX_CR(bank) GPO(((bank)*2) + GPIO_AXIQ_L0_CR1)
+#define AXIQ_LS_TX_CR(bank) GPO(((bank) * 2) + GPIO_AXIQ_L0_CR1)
 
 // -----------------------------------------------------------------------------
 // Status register:
 // -----------------------------------------------------------------------------
 
 //! @brief      AXIQ RX status register address.
-#define AXIQ_LS_RX_SR(bank) GPI(((bank)*3) + GPIO_AXIQ_L0_SR0)
+#define AXIQ_LS_RX_SR(bank) GPI(((bank) * 3) + GPIO_AXIQ_L0_SR0)
 
 //! @brief      AXIQ TX status register address.
-#define AXIQ_LS_TX_SR(bank) GPI(((bank)*3) + GPIO_AXIQ_L0_SR1)
+#define AXIQ_LS_TX_SR(bank) GPI(((bank) * 3) + GPIO_AXIQ_L0_SR1)
 
 //! @brief      DMA channel number for a given RX FIFO.
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ RX FIFO.
 //! @return     The DMA channel number for the RX FIFO @a fifo.
-#define AXIQ_LS_CHAN_RX(bank, fifo) (((bank)*5) + (fifo) + 1)
+#define AXIQ_LS_CHAN_RX(bank, fifo) (((bank) * 5) + (fifo) + 1)
 
 //! @brief      DMA channel mask for a given RX FIFO.
 //! @param      bank    specifies the AXIQ bank.
@@ -93,13 +93,13 @@ enum axiq_ls_bank_e {
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ RX FIFO.
 //! @return     The AXI address for the RX FIFO @a fifo.
-#define AXIQ_LS_ADDR_RX(bank, fifo) (BASE_AXIQ(bank) + ((fifo)*0x1000))
+#define AXIQ_LS_ADDR_RX(bank, fifo) (BASE_AXIQ(bank) + ((fifo) * 0x1000))
 
 //! @brief      DMA channel for a given TX FIFO.
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ TX FIFO.
 //! @return     The DMA channel number for the TX FIFO @a fifo.
-#define AXIQ_LS_CHAN_TX(bank, fifo) (((bank)*5) + (fifo) + 4)
+#define AXIQ_LS_CHAN_TX(bank, fifo) (((bank) * 5) + (fifo) + 4)
 
 //! @brief      DMA channel mask for a given TX FIFO.
 //! @param      bank    specifies the AXIQ bank.
@@ -116,7 +116,7 @@ enum axiq_ls_bank_e {
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ RX FIFO.
 //! @return     The AXI address for the RX FIFO @a fifo.
-#define AXIQ_LS_ADDR_TX(bank, fifo) (BASE_AXIQ(bank) + ((fifo)*0x1000))
+#define AXIQ_LS_ADDR_TX(bank, fifo) (BASE_AXIQ(bank) + ((fifo) * 0x1000))
 
 #include "axiq-ls.h"
 
@@ -156,7 +156,7 @@ enum axiq_hs_bank_e {
 #define AXIQ_HS_TX_SR(bank) GPI(GPIO_AXIQ_HS_SR1)
 
 //! @brief      HS AXIQ RX Max/Num/Sum GPIN.
-#define AXIQ_HS_RX_MAX_GPIN(bank) GPI(((bank)*2) + GPIO_AXIQ_HS_SR0)
+#define AXIQ_HS_RX_MAX_GPIN(bank) GPI(((bank) * 2) + GPIO_AXIQ_HS_SR0)
 
 //! @brief      DMA channel number for a given RX FIFO.
 //! @param      bank    specifies the AXIQ bank.
@@ -174,7 +174,7 @@ enum axiq_hs_bank_e {
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ RX FIFO.
 //! @return     The AXI address for the RX FIFO @a fifo.
-#define AXIQ_HS_ADDR_RX(bank, fifo) (BASE_AXIQ_HS + ((bank)*0x8000))
+#define AXIQ_HS_ADDR_RX(bank, fifo) (BASE_AXIQ_HS + ((bank) * 0x8000))
 
 //! @brief      DMA channel for a given TX FIFO.
 //! @param      bank    specifies the AXIQ bank.
@@ -192,7 +192,7 @@ enum axiq_hs_bank_e {
 //! @param      bank    specifies the AXIQ bank.
 //! @param      fifo    specifies the AXIQ TX FIFO.
 //! @return     The AXI address for the TX FIFO @a fifo.
-#define AXIQ_HS_ADDR_TX(bank, fifo) (BASE_AXIQ_HS + ((bank)*0x8000))
+#define AXIQ_HS_ADDR_TX(bank, fifo) (BASE_AXIQ_HS + ((bank) * 0x8000))
 
 #include "axiq-hs.h"
 #include "axiq-ls.h"