schematic clock diagram error #7
Description
Page 3 (clock diagram) of the schematic shows MCLK1/MCLK2 (AB34/P34) as LMS7002M inputs and FCLK1/FCLK2 (AA33/R29) as LMS7002M outputs.
This is opposite what is documented in the current LMS7002M datasheet (3.1r00) for these pins.
Perhaps the v2.4 schematic fixed this error, but per #5, this has not been uploaded.