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Copilot2bndy5
Copilot
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2bndy5
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refactor: wrap nRF24L01.h defines in nRF24L01 namespace
Agent-Logs-Url: https://github.com/nRF24/RF24/sessions/7ca3a7e2-a935-43a4-a67e-446bff9a6255 Co-authored-by: 2bndy5 <14963867+2bndy5@users.noreply.github.com>
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‎RF24.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@
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#include "RF24_config.h"
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#include "RF24.h"
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using namespace nRF24L01;
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/****************************************************************************/
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void RF24::csn(bool mode)

‎RF24.h‎

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@@ -16,6 +16,7 @@
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#define RF24_H_
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#include "RF24_config.h"
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#include "nRF24L01.h"
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#if defined(RF24_LINUX) || defined(LITTLEWIRE)
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#include "utility/includes.h"
@@ -139,17 +140,16 @@ typedef enum
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*/
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typedef enum
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{
142-
#include "nRF24L01.h"
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/// An alias of `0` to describe no IRQ events enabled.
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RF24_IRQ_NONE = 0,
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/// Represents an event where TX Data Failed to send.
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RF24_TX_DF = 1 << MASK_MAX_RT,
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RF24_TX_DF = 1 << nRF24L01::MASK_MAX_RT,
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/// Represents an event where TX Data Sent successfully.
148-
RF24_TX_DS = 1 << TX_DS,
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RF24_TX_DS = 1 << nRF24L01::TX_DS,
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/// Represents an event where RX Data is Ready to `RF24::read()`.
150-
RF24_RX_DR = 1 << RX_DR,
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RF24_RX_DR = 1 << nRF24L01::RX_DR,
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/// Equivalent to `RF24_RX_DR | RF24_TX_DS | RF24_TX_DF`.
152-
RF24_IRQ_ALL = (1 << MASK_MAX_RT) | (1 << TX_DS) | (1 << RX_DR),
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RF24_IRQ_ALL = (1 << nRF24L01::MASK_MAX_RT) | (1 << nRF24L01::TX_DS) | (1 << nRF24L01::RX_DR),
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} rf24_irq_flags_e;
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/**

‎nRF24L01.h‎

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Original file line numberDiff line numberDiff line change
@@ -23,106 +23,117 @@
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DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NRF24L01_H_
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#define NRF24L01_H_
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#include <stdint.h>
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namespace nRF24L01 {
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/* Memory Map */
27-
#define NRF_CONFIG 0x00
28-
#define EN_AA 0x01
29-
#define EN_RXADDR 0x02
30-
#define SETUP_AW 0x03
31-
#define SETUP_RETR 0x04
32-
#define RF_CH 0x05
33-
#define RF_SETUP 0x06
34-
#define NRF_STATUS 0x07
35-
#define OBSERVE_TX 0x08
36-
#define CD 0x09
37-
#define RX_ADDR_P0 0x0A
38-
#define RX_ADDR_P1 0x0B
39-
#define RX_ADDR_P2 0x0C
40-
#define RX_ADDR_P3 0x0D
41-
#define RX_ADDR_P4 0x0E
42-
#define RX_ADDR_P5 0x0F
43-
#define TX_ADDR 0x10
44-
#define RX_PW_P0 0x11
45-
#define RX_PW_P1 0x12
46-
#define RX_PW_P2 0x13
47-
#define RX_PW_P3 0x14
48-
#define RX_PW_P4 0x15
49-
#define RX_PW_P5 0x16
50-
#define FIFO_STATUS 0x17
51-
#define DYNPD 0x1C
52-
#define RF24_FEATURE 0x1D
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constexpr uint8_t NRF_CONFIG = 0x00;
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constexpr uint8_t EN_AA = 0x01;
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constexpr uint8_t EN_RXADDR = 0x02;
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constexpr uint8_t SETUP_AW = 0x03;
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constexpr uint8_t SETUP_RETR = 0x04;
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constexpr uint8_t RF_CH = 0x05;
40+
constexpr uint8_t RF_SETUP = 0x06;
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constexpr uint8_t NRF_STATUS = 0x07;
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constexpr uint8_t OBSERVE_TX = 0x08;
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constexpr uint8_t CD = 0x09;
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constexpr uint8_t RX_ADDR_P0 = 0x0A;
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constexpr uint8_t RX_ADDR_P1 = 0x0B;
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constexpr uint8_t RX_ADDR_P2 = 0x0C;
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constexpr uint8_t RX_ADDR_P3 = 0x0D;
48+
constexpr uint8_t RX_ADDR_P4 = 0x0E;
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constexpr uint8_t RX_ADDR_P5 = 0x0F;
50+
constexpr uint8_t TX_ADDR = 0x10;
51+
constexpr uint8_t RX_PW_P0 = 0x11;
52+
constexpr uint8_t RX_PW_P1 = 0x12;
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constexpr uint8_t RX_PW_P2 = 0x13;
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constexpr uint8_t RX_PW_P3 = 0x14;
55+
constexpr uint8_t RX_PW_P4 = 0x15;
56+
constexpr uint8_t RX_PW_P5 = 0x16;
57+
constexpr uint8_t FIFO_STATUS = 0x17;
58+
constexpr uint8_t DYNPD = 0x1C;
59+
constexpr uint8_t RF24_FEATURE = 0x1D;
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/* Bit Mnemonics */
55-
#define MASK_RX_DR 6
56-
#define MASK_TX_DS 5
57-
#define MASK_MAX_RT 4
58-
#define EN_CRC 3
59-
#define CRCO 2
60-
#define PWR_UP 1
61-
#define PRIM_RX 0
62-
#define ENAA_P5 5
63-
#define ENAA_P4 4
64-
#define ENAA_P3 3
65-
#define ENAA_P2 2
66-
#define ENAA_P1 1
67-
#define ENAA_P0 0
68-
#define ERX_P5 5
69-
#define ERX_P4 4
70-
#define ERX_P3 3
71-
#define ERX_P2 2
72-
#define ERX_P1 1
73-
#define ERX_P0 0
74-
#define AW 0
75-
#define ARD 4
76-
#define ARC 0
77-
#define PLL_LOCK 4
78-
#define CONT_WAVE 7
79-
#define RF_DR 3
80-
#define RF_PWR 6
81-
#define RX_DR 6
82-
#define TX_DS 5
83-
#define MAX_RT 4
84-
#define RX_P_NO 1
85-
#define TX_FULL 0
86-
#define PLOS_CNT 4
87-
#define ARC_CNT 0
88-
#define TX_REUSE 6
89-
#define FIFO_FULL 5
90-
#define TX_EMPTY 4
91-
#define RX_FULL 1
92-
#define RX_EMPTY 0
93-
#define DPL_P5 5
94-
#define DPL_P4 4
95-
#define DPL_P3 3
96-
#define DPL_P2 2
97-
#define DPL_P1 1
98-
#define DPL_P0 0
99-
#define EN_DPL 2
100-
#define EN_ACK_PAY 1
101-
#define EN_DYN_ACK 0
62+
constexpr uint8_t MASK_RX_DR = 6;
63+
constexpr uint8_t MASK_TX_DS = 5;
64+
constexpr uint8_t MASK_MAX_RT = 4;
65+
constexpr uint8_t EN_CRC = 3;
66+
constexpr uint8_t CRCO = 2;
67+
constexpr uint8_t PWR_UP = 1;
68+
constexpr uint8_t PRIM_RX = 0;
69+
constexpr uint8_t ENAA_P5 = 5;
70+
constexpr uint8_t ENAA_P4 = 4;
71+
constexpr uint8_t ENAA_P3 = 3;
72+
constexpr uint8_t ENAA_P2 = 2;
73+
constexpr uint8_t ENAA_P1 = 1;
74+
constexpr uint8_t ENAA_P0 = 0;
75+
constexpr uint8_t ERX_P5 = 5;
76+
constexpr uint8_t ERX_P4 = 4;
77+
constexpr uint8_t ERX_P3 = 3;
78+
constexpr uint8_t ERX_P2 = 2;
79+
constexpr uint8_t ERX_P1 = 1;
80+
constexpr uint8_t ERX_P0 = 0;
81+
constexpr uint8_t AW = 0;
82+
constexpr uint8_t ARD = 4;
83+
constexpr uint8_t ARC = 0;
84+
constexpr uint8_t PLL_LOCK = 4;
85+
constexpr uint8_t CONT_WAVE = 7;
86+
constexpr uint8_t RF_DR = 3;
87+
constexpr uint8_t RF_PWR = 6;
88+
constexpr uint8_t RX_DR = 6;
89+
constexpr uint8_t TX_DS = 5;
90+
constexpr uint8_t MAX_RT = 4;
91+
constexpr uint8_t RX_P_NO = 1;
92+
constexpr uint8_t TX_FULL = 0;
93+
constexpr uint8_t PLOS_CNT = 4;
94+
constexpr uint8_t ARC_CNT = 0;
95+
constexpr uint8_t TX_REUSE = 6;
96+
constexpr uint8_t FIFO_FULL = 5;
97+
constexpr uint8_t TX_EMPTY = 4;
98+
constexpr uint8_t RX_FULL = 1;
99+
constexpr uint8_t RX_EMPTY = 0;
100+
constexpr uint8_t DPL_P5 = 5;
101+
constexpr uint8_t DPL_P4 = 4;
102+
constexpr uint8_t DPL_P3 = 3;
103+
constexpr uint8_t DPL_P2 = 2;
104+
constexpr uint8_t DPL_P1 = 1;
105+
constexpr uint8_t DPL_P0 = 0;
106+
constexpr uint8_t EN_DPL = 2;
107+
constexpr uint8_t EN_ACK_PAY = 1;
108+
constexpr uint8_t EN_DYN_ACK = 0;
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103110
/* Instruction Mnemonics */
104-
#define R_REGISTER 0x00
105-
#define W_REGISTER 0x20
106-
#define REGISTER_MASK 0x1F
107-
#define ACTIVATE 0x50
108-
#define R_RX_PL_WID 0x60
109-
#define R_RX_PAYLOAD 0x61
110-
#define W_TX_PAYLOAD 0xA0
111-
#define W_ACK_PAYLOAD 0xA8
112-
#define FLUSH_TX 0xE1
113-
#define FLUSH_RX 0xE2
114-
#define REUSE_TX_PL 0xE3
115-
#define RF24_NOP 0xFF
111+
constexpr uint8_t R_REGISTER = 0x00;
112+
constexpr uint8_t W_REGISTER = 0x20;
113+
constexpr uint8_t REGISTER_MASK = 0x1F;
114+
constexpr uint8_t ACTIVATE = 0x50;
115+
constexpr uint8_t R_RX_PL_WID = 0x60;
116+
constexpr uint8_t R_RX_PAYLOAD = 0x61;
117+
constexpr uint8_t W_TX_PAYLOAD = 0xA0;
118+
constexpr uint8_t W_ACK_PAYLOAD = 0xA8;
119+
constexpr uint8_t FLUSH_TX = 0xE1;
120+
constexpr uint8_t FLUSH_RX = 0xE2;
121+
constexpr uint8_t REUSE_TX_PL = 0xE3;
122+
constexpr uint8_t RF24_NOP = 0xFF;
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117124
/* Non-P omissions */
118-
#define LNA_HCURR 0
125+
constexpr uint8_t LNA_HCURR = 0;
119126

120127
/* P model memory Map */
121-
#define RPD 0x09
122-
#define W_TX_PAYLOAD_NO_ACK 0xB0
128+
constexpr uint8_t RPD = 0x09;
129+
constexpr uint8_t W_TX_PAYLOAD_NO_ACK = 0xB0;
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124131
/* P model bit Mnemonics */
125-
#define RF_DR_LOW 5
126-
#define RF_DR_HIGH 3
127-
#define RF_PWR_LOW 1
128-
#define RF_PWR_HIGH 2
132+
constexpr uint8_t RF_DR_LOW = 5;
133+
constexpr uint8_t RF_DR_HIGH = 3;
134+
constexpr uint8_t RF_PWR_LOW = 1;
135+
constexpr uint8_t RF_PWR_HIGH = 2;
136+
137+
} // namespace nRF24L01
138+
139+
#endif // NRF24L01_H_

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