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31 | 31 | namespace nRF24L01 { |
32 | 32 |
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33 | 33 | /* Memory Map */ |
34 | | -constexpr uint8_t CONFIG = 0x00; |
35 | | -constexpr uint8_t EN_AA = 0x01; |
36 | | -constexpr uint8_t EN_RXADDR = 0x02; |
37 | | -constexpr uint8_t SETUP_AW = 0x03; |
38 | | -constexpr uint8_t SETUP_RETR = 0x04; |
39 | | -constexpr uint8_t RF_CH = 0x05; |
40 | | -constexpr uint8_t RF_SETUP = 0x06; |
41 | | -constexpr uint8_t STATUS = 0x07; |
42 | | -constexpr uint8_t OBSERVE_TX = 0x08; |
43 | | -constexpr uint8_t CD = 0x09; |
44 | | -constexpr uint8_t RX_ADDR_P0 = 0x0A; |
45 | | -constexpr uint8_t RX_ADDR_P1 = 0x0B; |
46 | | -constexpr uint8_t RX_ADDR_P2 = 0x0C; |
47 | | -constexpr uint8_t RX_ADDR_P3 = 0x0D; |
48 | | -constexpr uint8_t RX_ADDR_P4 = 0x0E; |
49 | | -constexpr uint8_t RX_ADDR_P5 = 0x0F; |
50 | | -constexpr uint8_t TX_ADDR = 0x10; |
51 | | -constexpr uint8_t RX_PW_P0 = 0x11; |
52 | | -constexpr uint8_t RX_PW_P1 = 0x12; |
53 | | -constexpr uint8_t RX_PW_P2 = 0x13; |
54 | | -constexpr uint8_t RX_PW_P3 = 0x14; |
55 | | -constexpr uint8_t RX_PW_P4 = 0x15; |
56 | | -constexpr uint8_t RX_PW_P5 = 0x16; |
| 34 | +constexpr uint8_t CONFIG = 0x00; |
| 35 | +constexpr uint8_t EN_AA = 0x01; |
| 36 | +constexpr uint8_t EN_RXADDR = 0x02; |
| 37 | +constexpr uint8_t SETUP_AW = 0x03; |
| 38 | +constexpr uint8_t SETUP_RETR = 0x04; |
| 39 | +constexpr uint8_t RF_CH = 0x05; |
| 40 | +constexpr uint8_t RF_SETUP = 0x06; |
| 41 | +constexpr uint8_t STATUS = 0x07; |
| 42 | +constexpr uint8_t OBSERVE_TX = 0x08; |
| 43 | +constexpr uint8_t CD = 0x09; |
| 44 | +constexpr uint8_t RX_ADDR_P0 = 0x0A; |
| 45 | +constexpr uint8_t RX_ADDR_P1 = 0x0B; |
| 46 | +constexpr uint8_t RX_ADDR_P2 = 0x0C; |
| 47 | +constexpr uint8_t RX_ADDR_P3 = 0x0D; |
| 48 | +constexpr uint8_t RX_ADDR_P4 = 0x0E; |
| 49 | +constexpr uint8_t RX_ADDR_P5 = 0x0F; |
| 50 | +constexpr uint8_t TX_ADDR = 0x10; |
| 51 | +constexpr uint8_t RX_PW_P0 = 0x11; |
| 52 | +constexpr uint8_t RX_PW_P1 = 0x12; |
| 53 | +constexpr uint8_t RX_PW_P2 = 0x13; |
| 54 | +constexpr uint8_t RX_PW_P3 = 0x14; |
| 55 | +constexpr uint8_t RX_PW_P4 = 0x15; |
| 56 | +constexpr uint8_t RX_PW_P5 = 0x16; |
57 | 57 | constexpr uint8_t FIFO_STATUS = 0x17; |
58 | | -constexpr uint8_t DYNPD = 0x1C; |
59 | | -constexpr uint8_t FEATURE = 0x1D; |
| 58 | +constexpr uint8_t DYNPD = 0x1C; |
| 59 | +constexpr uint8_t FEATURE = 0x1D; |
60 | 60 |
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61 | 61 | /* Bit Mnemonics */ |
62 | | -constexpr uint8_t MASK_RX_DR = 6; |
63 | | -constexpr uint8_t MASK_TX_DS = 5; |
| 62 | +constexpr uint8_t MASK_RX_DR = 6; |
| 63 | +constexpr uint8_t MASK_TX_DS = 5; |
64 | 64 | constexpr uint8_t MASK_MAX_RT = 4; |
65 | | -constexpr uint8_t EN_CRC = 3; |
66 | | -constexpr uint8_t CRCO = 2; |
67 | | -constexpr uint8_t PWR_UP = 1; |
68 | | -constexpr uint8_t PRIM_RX = 0; |
69 | | -constexpr uint8_t ENAA_P5 = 5; |
70 | | -constexpr uint8_t ENAA_P4 = 4; |
71 | | -constexpr uint8_t ENAA_P3 = 3; |
72 | | -constexpr uint8_t ENAA_P2 = 2; |
73 | | -constexpr uint8_t ENAA_P1 = 1; |
74 | | -constexpr uint8_t ENAA_P0 = 0; |
75 | | -constexpr uint8_t ERX_P5 = 5; |
76 | | -constexpr uint8_t ERX_P4 = 4; |
77 | | -constexpr uint8_t ERX_P3 = 3; |
78 | | -constexpr uint8_t ERX_P2 = 2; |
79 | | -constexpr uint8_t ERX_P1 = 1; |
80 | | -constexpr uint8_t ERX_P0 = 0; |
81 | | -constexpr uint8_t AW = 0; |
82 | | -constexpr uint8_t ARD = 4; |
83 | | -constexpr uint8_t ARC = 0; |
84 | | -constexpr uint8_t PLL_LOCK = 4; |
85 | | -constexpr uint8_t CONT_WAVE = 7; |
86 | | -constexpr uint8_t RF_DR = 3; |
87 | | -constexpr uint8_t RF_PWR = 6; |
88 | | -constexpr uint8_t RX_DR = 6; |
89 | | -constexpr uint8_t TX_DS = 5; |
90 | | -constexpr uint8_t MAX_RT = 4; |
91 | | -constexpr uint8_t RX_P_NO = 1; |
92 | | -constexpr uint8_t TX_FULL = 0; |
93 | | -constexpr uint8_t PLOS_CNT = 4; |
94 | | -constexpr uint8_t ARC_CNT = 0; |
95 | | -constexpr uint8_t TX_REUSE = 6; |
96 | | -constexpr uint8_t FIFO_FULL = 5; |
97 | | -constexpr uint8_t TX_EMPTY = 4; |
98 | | -constexpr uint8_t RX_FULL = 1; |
99 | | -constexpr uint8_t RX_EMPTY = 0; |
100 | | -constexpr uint8_t DPL_P5 = 5; |
101 | | -constexpr uint8_t DPL_P4 = 4; |
102 | | -constexpr uint8_t DPL_P3 = 3; |
103 | | -constexpr uint8_t DPL_P2 = 2; |
104 | | -constexpr uint8_t DPL_P1 = 1; |
105 | | -constexpr uint8_t DPL_P0 = 0; |
106 | | -constexpr uint8_t EN_DPL = 2; |
107 | | -constexpr uint8_t EN_ACK_PAY = 1; |
108 | | -constexpr uint8_t EN_DYN_ACK = 0; |
| 65 | +constexpr uint8_t EN_CRC = 3; |
| 66 | +constexpr uint8_t CRCO = 2; |
| 67 | +constexpr uint8_t PWR_UP = 1; |
| 68 | +constexpr uint8_t PRIM_RX = 0; |
| 69 | +constexpr uint8_t ENAA_P5 = 5; |
| 70 | +constexpr uint8_t ENAA_P4 = 4; |
| 71 | +constexpr uint8_t ENAA_P3 = 3; |
| 72 | +constexpr uint8_t ENAA_P2 = 2; |
| 73 | +constexpr uint8_t ENAA_P1 = 1; |
| 74 | +constexpr uint8_t ENAA_P0 = 0; |
| 75 | +constexpr uint8_t ERX_P5 = 5; |
| 76 | +constexpr uint8_t ERX_P4 = 4; |
| 77 | +constexpr uint8_t ERX_P3 = 3; |
| 78 | +constexpr uint8_t ERX_P2 = 2; |
| 79 | +constexpr uint8_t ERX_P1 = 1; |
| 80 | +constexpr uint8_t ERX_P0 = 0; |
| 81 | +constexpr uint8_t AW = 0; |
| 82 | +constexpr uint8_t ARD = 4; |
| 83 | +constexpr uint8_t ARC = 0; |
| 84 | +constexpr uint8_t PLL_LOCK = 4; |
| 85 | +constexpr uint8_t CONT_WAVE = 7; |
| 86 | +constexpr uint8_t RF_DR = 3; |
| 87 | +constexpr uint8_t RF_PWR = 6; |
| 88 | +constexpr uint8_t RX_DR = 6; |
| 89 | +constexpr uint8_t TX_DS = 5; |
| 90 | +constexpr uint8_t MAX_RT = 4; |
| 91 | +constexpr uint8_t RX_P_NO = 1; |
| 92 | +constexpr uint8_t TX_FULL = 0; |
| 93 | +constexpr uint8_t PLOS_CNT = 4; |
| 94 | +constexpr uint8_t ARC_CNT = 0; |
| 95 | +constexpr uint8_t TX_REUSE = 6; |
| 96 | +constexpr uint8_t FIFO_FULL = 5; |
| 97 | +constexpr uint8_t TX_EMPTY = 4; |
| 98 | +constexpr uint8_t RX_FULL = 1; |
| 99 | +constexpr uint8_t RX_EMPTY = 0; |
| 100 | +constexpr uint8_t DPL_P5 = 5; |
| 101 | +constexpr uint8_t DPL_P4 = 4; |
| 102 | +constexpr uint8_t DPL_P3 = 3; |
| 103 | +constexpr uint8_t DPL_P2 = 2; |
| 104 | +constexpr uint8_t DPL_P1 = 1; |
| 105 | +constexpr uint8_t DPL_P0 = 0; |
| 106 | +constexpr uint8_t EN_DPL = 2; |
| 107 | +constexpr uint8_t EN_ACK_PAY = 1; |
| 108 | +constexpr uint8_t EN_DYN_ACK = 0; |
109 | 109 |
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110 | 110 | /* Instruction Mnemonics */ |
111 | | -constexpr uint8_t R_REGISTER = 0x00; |
112 | | -constexpr uint8_t W_REGISTER = 0x20; |
| 111 | +constexpr uint8_t R_REGISTER = 0x00; |
| 112 | +constexpr uint8_t W_REGISTER = 0x20; |
113 | 113 | constexpr uint8_t REGISTER_MASK = 0x1F; |
114 | | -constexpr uint8_t ACTIVATE = 0x50; |
115 | | -constexpr uint8_t R_RX_PL_WID = 0x60; |
116 | | -constexpr uint8_t R_RX_PAYLOAD = 0x61; |
117 | | -constexpr uint8_t W_TX_PAYLOAD = 0xA0; |
| 114 | +constexpr uint8_t ACTIVATE = 0x50; |
| 115 | +constexpr uint8_t R_RX_PL_WID = 0x60; |
| 116 | +constexpr uint8_t R_RX_PAYLOAD = 0x61; |
| 117 | +constexpr uint8_t W_TX_PAYLOAD = 0xA0; |
118 | 118 | constexpr uint8_t W_ACK_PAYLOAD = 0xA8; |
119 | | -constexpr uint8_t FLUSH_TX = 0xE1; |
120 | | -constexpr uint8_t FLUSH_RX = 0xE2; |
121 | | -constexpr uint8_t REUSE_TX_PL = 0xE3; |
122 | | -constexpr uint8_t RF24_NOP = 0xFF; |
| 119 | +constexpr uint8_t FLUSH_TX = 0xE1; |
| 120 | +constexpr uint8_t FLUSH_RX = 0xE2; |
| 121 | +constexpr uint8_t REUSE_TX_PL = 0xE3; |
| 122 | +constexpr uint8_t RF24_NOP = 0xFF; |
123 | 123 |
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124 | 124 | /* Non-P omissions */ |
125 | 125 | constexpr uint8_t LNA_HCURR = 0; |
126 | 126 |
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127 | 127 | /* P model memory Map */ |
128 | | -constexpr uint8_t RPD = 0x09; |
| 128 | +constexpr uint8_t RPD = 0x09; |
129 | 129 | constexpr uint8_t W_TX_PAYLOAD_NO_ACK = 0xB0; |
130 | 130 |
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131 | 131 | /* P model bit Mnemonics */ |
132 | | -constexpr uint8_t RF_DR_LOW = 5; |
133 | | -constexpr uint8_t RF_DR_HIGH = 3; |
134 | | -constexpr uint8_t RF_PWR_LOW = 1; |
| 132 | +constexpr uint8_t RF_DR_LOW = 5; |
| 133 | +constexpr uint8_t RF_DR_HIGH = 3; |
| 134 | +constexpr uint8_t RF_PWR_LOW = 1; |
135 | 135 | constexpr uint8_t RF_PWR_HIGH = 2; |
136 | 136 |
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137 | 137 | } // namespace nRF24L01 |
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