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Makefile
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44 lines (36 loc) · 722 Bytes
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CC=gcc
CXX=g++
CFLAGS=-g -Wall -O2 -I..
CXXFLAGS=$(CFLAGS)
LIBS=klib.a
all:$(LIBS)
clean:
rm -fr $(LIBS) *.o
LSOURCES = \
ksa.c \
khmm.c \
kson.h \
kmath.c \
kstring.c \
keigen.c \
knetfile.c \
ksw.c \
knhx.c \
bgzf.c \
kexpr.c \
kthread.c \
kopen.c \
kurl.c \
kalloc.c
LOBJECTS = ${LSOURCES:.c=.o}
# That archive depends on all the "LOBJECTS"
klib.a : ${LOBJECTS}
${AR} crf $@ $^
# This implicit rule tells how make is supposed to produce an object
# file (.o suffix) from a C file (.c suffix). This is needed to
# produce an executable file from your program.
#
# Here the make-special variable $< expands and to the dependency (the
# .o object file).
.c.o :
${CC} ${CFLAGS} -c $<