Skip to content

Commit bea597b

Browse files
josesimoesjosesimoes
authored
Improve details for STM32 devices (#74)
***NO_CI***
1 parent f0dc2b6 commit bea597b

File tree

70 files changed

+52016
-55
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

70 files changed

+52016
-55
lines changed

‎lib/stlink/Data_Base/STM32_Prog_DB_0x410.xml‎

Lines changed: 475 additions & 0 deletions
Large diffs are not rendered by default.

‎lib/stlink/Data_Base/STM32_Prog_DB_0x411.xml‎

Lines changed: 406 additions & 0 deletions
Large diffs are not rendered by default.

‎lib/stlink/Data_Base/STM32_Prog_DB_0x412.xml‎

Lines changed: 399 additions & 0 deletions
Large diffs are not rendered by default.

‎lib/stlink/Data_Base/STM32_Prog_DB_0x413.xml‎

Lines changed: 322 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,322 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
3+
<Device>
4+
<DeviceID>0x413</DeviceID>
5+
<Vendor>STMicroelectronics</Vendor>
6+
<Type>MCU</Type>
7+
<CPU>Cortex-M4</CPU>
8+
<Name>STM32F405xx/F407xx/F415xx/F417xx</Name>
9+
<Series>STM32F4</Series>
10+
<Description>ARM 32-bit Cortex-M4 based device</Description>
11+
<Configurations>
12+
<!-- JTAG_SWD Interface -->
13+
<Interface name="JTAG_SWD"/>
14+
<!-- Bootloader Interface -->
15+
<Interface name="Bootloader"/>
16+
</Configurations>
17+
<!-- Peripherals -->
18+
<Peripherals>
19+
<!-- Embedded SRAM -->
20+
<Peripheral>
21+
<Name>Embedded SRAM</Name>
22+
<Type>Storage</Type>
23+
<Description/>
24+
<ErasedValue>0x00</ErasedValue>
25+
<Access>RWE</Access>
26+
<!-- 112 KB 0x1c000-->
27+
<Configuration>
28+
<Parameters address="0x20000000" name="SRAM" size="0x20000"/>
29+
<Description/>
30+
<Organization>Single</Organization>
31+
<Bank name="Bank 1">
32+
<Field>
33+
<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x20000"/>
34+
</Field>
35+
</Bank>
36+
</Configuration>
37+
</Peripheral>
38+
<!-- Embedded Flash -->
39+
<Peripheral>
40+
<Name>Embedded Flash</Name>
41+
<Type>Storage</Type>
42+
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
43+
<ErasedValue>0xFF</ErasedValue>
44+
<Access>RWE</Access>
45+
<FlashSize address="0x1FFFF7CC" default="0x100000"/>
46+
<!-- 1024KB Single Bank -->
47+
<Configuration>
48+
<Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
49+
<Description/>
50+
<Organization>Single</Organization>
51+
<Allignement>0x4</Allignement>
52+
<Bank name="Bank 1">
53+
<Field>
54+
<Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
55+
</Field>
56+
<Field>
57+
<Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
58+
</Field>
59+
<Field>
60+
<Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
61+
</Field>
62+
</Bank>
63+
</Configuration>
64+
</Peripheral>
65+
<!-- OTP -->
66+
<Peripheral>
67+
<Name>OTP</Name>
68+
<Type>Storage</Type>
69+
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
70+
<ErasedValue>0xFF</ErasedValue>
71+
<Access>RW</Access>
72+
<!-- 512 Bytes single bank -->
73+
<Configuration>
74+
<Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
75+
<Description/>
76+
<Organization>Single</Organization>
77+
<Allignement>0x4</Allignement>
78+
<Bank name="OTP">
79+
<Field>
80+
<Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
81+
</Field>
82+
</Bank>
83+
</Configuration>
84+
</Peripheral>
85+
<!-- Mirror Option Bytes -->
86+
<Peripheral>
87+
<Name>MirrorOptionBytes</Name>
88+
<Type>Storage</Type>
89+
<Description>Mirror Option Bytes contains the extra area.</Description>
90+
<ErasedValue>0xFF</ErasedValue>
91+
<Access>RW</Access>
92+
<!-- 8 Bytes single bank -->
93+
<Configuration>
94+
<Parameters address="0x1FFFC000" name=" 8 Bytes Data MirrorOptionBytes" size="0x8"/>
95+
<Description/>
96+
<Organization>Single</Organization>
97+
<Allignement>0x4</Allignement>
98+
<Bank name="MirrorOptionBytes">
99+
<Field>
100+
<Parameters address="0x1FFFC000" name="MirrorOptionBytes" occurence="0x1" size="0x8"/>
101+
</Field>
102+
</Bank>
103+
</Configuration>
104+
</Peripheral>
105+
<!-- Option Bytes -->
106+
<Peripheral>
107+
<Name>Option Bytes</Name>
108+
<Type>Configuration</Type>
109+
<Description/>
110+
<Access>RW</Access>
111+
<Bank interface="JTAG_SWD">
112+
<Parameters address="0x40023c14" name="Bank 1" size="0x4"/>
113+
<Category>
114+
<Name>Read Out Protection</Name>
115+
<Field>
116+
<Parameters address="0x40023c14" name="RDP" size="0x4"/>
117+
<AssignedBits>
118+
<Bit>
119+
<Name>RDP</Name>
120+
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
121+
<BitOffset>0x8</BitOffset>
122+
<BitWidth>0x8</BitWidth>
123+
<Access>RW</Access>
124+
<Values>
125+
<Val value="0xAA">Level 0, no protection</Val>
126+
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
127+
<Val value="0xCC">Level 2, chip protection</Val>
128+
</Values>
129+
</Bit>
130+
</AssignedBits>
131+
</Field>
132+
</Category>
133+
<Category>
134+
<Name>BOR Level</Name>
135+
<Field>
136+
<Parameters address="0x40023c14" name="USER" size="0x4"/>
137+
<AssignedBits>
138+
<Bit>
139+
<Name>BOR_LEV</Name>
140+
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
141+
<BitOffset>0x2</BitOffset>
142+
<BitWidth>0x2</BitWidth>
143+
<Access>RW</Access>
144+
<Values>
145+
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
146+
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
147+
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
148+
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
149+
</Values>
150+
</Bit>
151+
</AssignedBits>
152+
</Field>
153+
</Category>
154+
<Category>
155+
<Name>User Configuration</Name>
156+
<Field>
157+
<Parameters address="0x40023c14" name="USER" size="0x4"/>
158+
<AssignedBits>
159+
<Bit>
160+
<Name>WDG_SW</Name>
161+
<Description/>
162+
<BitOffset>0x5</BitOffset>
163+
<BitWidth>0x1</BitWidth>
164+
<Access>RW</Access>
165+
<Values>
166+
<Val value="0x0">Hardware watchdog</Val>
167+
<Val value="0x1">Software watchdog</Val>
168+
</Values>
169+
</Bit>
170+
<Bit>
171+
<Name>nRST_STOP</Name>
172+
<Description/>
173+
<BitOffset>0x6</BitOffset>
174+
<BitWidth>0x1</BitWidth>
175+
<Access>RW</Access>
176+
<Values>
177+
<Val value="0x0">Reset generated when entering Stop mode</Val>
178+
<Val value="0x1">No reset generated</Val>
179+
</Values>
180+
</Bit>
181+
<Bit>
182+
<Name>nRST_STDBY</Name>
183+
<Description/>
184+
<BitOffset>0x7</BitOffset>
185+
<BitWidth>0x1</BitWidth>
186+
<Access>RW</Access>
187+
<Values>
188+
<Val value="0x0">Reset generated when entering Standby mode</Val>
189+
<Val value="0x1">No reset generated</Val>
190+
</Values>
191+
</Bit>
192+
</AssignedBits>
193+
</Field>
194+
</Category>
195+
<Category>
196+
<Name>Write Protection</Name>
197+
<Field>
198+
<Parameters address="0x40023c14" name="WRP1" size="0x4"/>
199+
<AssignedBits>
200+
<Bit>
201+
<Name>WRP0</Name>
202+
<Description/>
203+
<BitOffset>0x10</BitOffset>
204+
<BitWidth>0xC</BitWidth>
205+
<Access>RW</Access>
206+
<Values ByBit="true">
207+
<Val value="0x0">Write protection active</Val>
208+
<Val value="0x1">Write protection not active</Val>
209+
</Values>
210+
</Bit>
211+
</AssignedBits>
212+
</Field>
213+
</Category>
214+
</Bank>
215+
<Bank interface="Bootloader">
216+
<Parameters address="0x1FFFC000" name="Bank 1" size="0x8"/>
217+
<Category>
218+
<Name>Read Out Protection</Name>
219+
<Field>
220+
<Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
221+
<AssignedBits>
222+
<Bit>
223+
<Name>RDP</Name>
224+
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
225+
<BitOffset>0x8</BitOffset>
226+
<BitWidth>0x8</BitWidth>
227+
<Access>RW</Access>
228+
<Values>
229+
<Val value="0xAA">Level 0, no protection</Val>
230+
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
231+
<Val value="0xCC">Level 2, chip protection</Val>
232+
</Values>
233+
</Bit>
234+
</AssignedBits>
235+
</Field>
236+
</Category>
237+
<Category>
238+
<Name>BOR Level</Name>
239+
<Field>
240+
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
241+
<AssignedBits>
242+
<Bit>
243+
<Name>BOR_LEV</Name>
244+
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
245+
<BitOffset>0x2</BitOffset>
246+
<BitWidth>0x2</BitWidth>
247+
<Access>RW</Access>
248+
<Values>
249+
<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
250+
<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
251+
<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
252+
<Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
253+
</Values>
254+
</Bit>
255+
</AssignedBits>
256+
</Field>
257+
</Category>
258+
<Category>
259+
<Name>User Configuration</Name>
260+
<Field>
261+
<Parameters address="0x1FFFC000" name="USER" size="0x4"/>
262+
<AssignedBits>
263+
<Bit>
264+
<Name>WDG_SW</Name>
265+
<Description/>
266+
<BitOffset>0x5</BitOffset>
267+
<BitWidth>0x1</BitWidth>
268+
<Access>RW</Access>
269+
<Values>
270+
<Val value="0x0">Hardware watchdog</Val>
271+
<Val value="0x1">Software watchdog</Val>
272+
</Values>
273+
</Bit>
274+
<Bit>
275+
<Name>nRST_STOP</Name>
276+
<Description/>
277+
<BitOffset>0x6</BitOffset>
278+
<BitWidth>0x1</BitWidth>
279+
<Access>RW</Access>
280+
<Values>
281+
<Val value="0x0">Reset generated when entering Stop mode</Val>
282+
<Val value="0x1">No reset generated</Val>
283+
</Values>
284+
</Bit>
285+
<Bit>
286+
<Name>nRST_STDBY</Name>
287+
<Description/>
288+
<BitOffset>0x7</BitOffset>
289+
<BitWidth>0x1</BitWidth>
290+
<Access>RW</Access>
291+
<Values>
292+
<Val value="0x0">Reset generated when entering Standby mode</Val>
293+
<Val value="0x1">No reset generated</Val>
294+
</Values>
295+
</Bit>
296+
</AssignedBits>
297+
</Field>
298+
</Category>
299+
<Category>
300+
<Name>Write Protection</Name>
301+
<Field>
302+
<Parameters address="0x1FFFC008" name="WRP1" size="0x4"/>
303+
<AssignedBits>
304+
<Bit>
305+
<Name>WRP0</Name>
306+
<Description/>
307+
<BitOffset>0x0</BitOffset>
308+
<BitWidth>0xC</BitWidth>
309+
<Access>RW</Access>
310+
<Values ByBit="true">
311+
<Val value="0x0">Write protection active</Val>
312+
<Val value="0x1">Write protection not active</Val>
313+
</Values>
314+
</Bit>
315+
</AssignedBits>
316+
</Field>
317+
</Category>
318+
</Bank>
319+
</Peripheral>
320+
</Peripherals>
321+
</Device>
322+
</Root>

0 commit comments

Comments
 (0)