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‎targets/ChibiOS/ORGPAL_PALTHREE/target_external_memory.c‎

Lines changed: 47 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,6 @@
77
#include "hal.h"
88
#include "fsmc_sdram_lld.h"
99

10-
1110
// SDRAM Mode definition register defines
1211
#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
1312
#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
@@ -22,81 +21,73 @@
2221
#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
2322

2423
// FMC_ReadPipe_Delay
25-
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
26-
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
27-
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
28-
#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
24+
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
25+
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
26+
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
27+
#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
2928

3029
// FMC_Read_Burst
31-
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
32-
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
33-
#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
30+
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
31+
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
32+
#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
3433

3534
// FMC_SDClock_Period
36-
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
37-
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
38-
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
39-
#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
35+
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
36+
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
37+
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
38+
#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
4039

4140
// FMC_ColumnBits_Number
42-
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
43-
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
44-
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
45-
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
41+
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
42+
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
43+
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
44+
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
4645

4746
// FMC_RowBits_Number
48-
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
49-
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
50-
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
47+
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
48+
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
49+
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
5150

5251
// FMC_SDMemory_Data_Width
53-
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
54-
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
55-
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
52+
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
53+
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
54+
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
5655

5756
// FMC_InternalBank_Number
58-
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
59-
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
57+
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
58+
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
6059

6160
// FMC_CAS_Latency
62-
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
63-
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
64-
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
61+
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
62+
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
63+
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
6564

6665
// FMC_Write_Protection
67-
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
68-
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
69-
70-
#define SDRAM_SIZE (8 * 1024 * 1024)
71-
#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE)
66+
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
67+
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
7268

69+
#define SDRAM_SIZE (8 * 1024 * 1024)
70+
#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE)
7371

7472
// SDRAM driver configuration structure.
7573
static const SDRAMConfig sdram_cfg = {
76-
.sdcr = (uint32_t) FMC_ColumnBits_Number_8b |
77-
FMC_RowBits_Number_12b |
78-
FMC_SDMemory_Width_16b |
79-
FMC_InternalBank_Number_4 |
80-
FMC_CAS_Latency_3 |
81-
FMC_Write_Protection_Disable |
82-
FMC_SDClock_Period_2 |
83-
FMC_Read_Burst_Enable |
84-
FMC_ReadPipe_Delay_1,
85-
.sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
86-
(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
87-
(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
88-
(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
89-
(3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
90-
(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
91-
(2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
92-
// NRFS = 4-1
93-
.sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 |
94-
FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
95-
FMC_SDCMR_MRD_CAS_LATENCY_3 |
96-
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
97-
FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9,
98-
99-
.sdrtr = (uint32_t)(683 << 1),
74+
.sdcr = (uint32_t)FMC_ColumnBits_Number_8b | FMC_RowBits_Number_12b | FMC_SDMemory_Width_16b |
75+
FMC_InternalBank_Number_4 | FMC_CAS_Latency_3 | FMC_Write_Protection_Disable | FMC_SDClock_Period_2 |
76+
FMC_Read_Burst_Enable | FMC_ReadPipe_Delay_1,
77+
.sdtr = (uint32_t)(2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
78+
(7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
79+
(4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
80+
(7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
81+
(3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
82+
(2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
83+
(2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
84+
// NRFS = 4-1
85+
.sdcmr =
86+
(3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | FMC_SDCMR_MRD_CAS_LATENCY_3 |
87+
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE)
88+
<< 9,
89+
90+
.sdrtr = (uint32_t)(683 << 1),
10091
};
10192

10293
void Target_ExternalMemoryInit()

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