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Properly offset managed SPI bus ID to native for ESP32C3 and S3 (#2915)
1 parent 6a56d84 commit 96ce46a

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2 files changed

+12
-4
lines changed

2 files changed

+12
-4
lines changed

targets/ESP32/_common/Target_Windows_Storage.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -160,8 +160,10 @@ bool Storage_MountSpi(int spiBus, uint32_t csPin, int driveIndex)
160160

161161
sdmmc_host_t host = SDSPI_HOST_DEFAULT();
162162
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
163-
host.slot = spiBus;
163+
// First available bus on ESP32_C3/S3 is SPI2_HOST
164+
host.slot = spiBus + SPI2_HOST;
164165
#else
166+
// First available bus on ESP32 is HSPI_HOST(1)
165167
host.slot = spiBus + HSPI_HOST;
166168
#endif
167169

targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -189,8 +189,10 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev
189189
if (ret != ESP_OK)
190190
{
191191
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
192-
ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex, ret);
192+
// First available bus on ESP32_C3/S3 is SPI2_HOST
193+
ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + SPI2_HOST, ret);
193194
#else
195+
// First available bus on ESP32 is HSPI_HOST(1)
194196
ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + HSPI_HOST, ret);
195197
#endif
196198
return false;
@@ -208,16 +210,20 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev
208210
bool CPU_SPI_Uninitialize(uint8_t busIndex)
209211
{
210212
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
211-
esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex));
213+
// First available bus on ESP32_C3/S3 is SPI2_HOST
214+
esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + SPI2_HOST));
212215
#else
216+
// First available bus on ESP32 is HSPI_HOST(1)
213217
esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + HSPI_HOST));
214218
#endif
215219

216220
if (ret != ESP_OK)
217221
{
218222
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3)
219-
ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex, ret);
223+
// First available bus on ESP32_C3/S3 is SPI2_HOST
224+
ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + SPI2_HOST, ret);
220225
#else
226+
// First available bus on ESP32 is HSPI_HOST(1)
221227
ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + HSPI_HOST, ret);
222228
#endif
223229

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