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[RISCV] Add attribute vscale_range(2,1024) to the tests for removing zero_extend on RV64. NFC (llvm#131973)
The attribute `vscale_range(2,1024)` is added to each function by default when the V extension is enabled, so that the zero_extend for the i32 %evl to i64 on RV64 would be removed usually.
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‎llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll‎

Lines changed: 9 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1425,32 +1425,15 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
14251425
ret <vscale x 32 x i32> %v
14261426
}
14271427

1428-
; FIXME: The upper half of the operation is doing nothing but we don't catch
1429-
; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16)
1430-
; (the "original" %evl is the "and", due to known-bits issues with legalizing
1431-
; the i32 %evl to i64) and this isn't detected as 0.
1432-
; This could be resolved in the future with more detailed KnownBits analysis
1433-
; for ISD::VSCALE.
1434-
1435-
define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) {
1436-
; RV32-LABEL: vadd_vi_nxv32i32_evl_nx16:
1437-
; RV32: # %bb.0:
1438-
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1439-
; RV32-NEXT: vadd.vi v8, v8, -1, v0.t
1440-
; RV32-NEXT: ret
1441-
;
1442-
; RV64-LABEL: vadd_vi_nxv32i32_evl_nx16:
1443-
; RV64: # %bb.0:
1444-
; RV64-NEXT: csrr a0, vlenb
1445-
; RV64-NEXT: srli a0, a0, 2
1446-
; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
1447-
; RV64-NEXT: vslidedown.vx v24, v0, a0
1448-
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1449-
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
1450-
; RV64-NEXT: vmv1r.v v0, v24
1451-
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma
1452-
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
1453-
; RV64-NEXT: ret
1428+
; The attribute vscale_range(2,1024) given here can remove the zero_extend for
1429+
; the i32 %evl to i64 on RV64 through KnownBits analysis.
1430+
1431+
define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) vscale_range(2,1024) {
1432+
; CHECK-LABEL: vadd_vi_nxv32i32_evl_nx16:
1433+
; CHECK: # %bb.0:
1434+
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1435+
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
1436+
; CHECK-NEXT: ret
14541437
%evl = call i32 @llvm.vscale.i32()
14551438
%evl0 = mul i32 %evl, 16
14561439
%v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl0)

‎llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll‎

Lines changed: 9 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,32 +1060,15 @@ define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
10601060
ret <vscale x 32 x i32> %v
10611061
}
10621062

1063-
; FIXME: The upper half of the operation is doing nothing but we don't catch
1064-
; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16)
1065-
; (the "original" %evl is the "and", due to known-bits issues with legalizing
1066-
; the i32 %evl to i64) and this isn't detected as 0.
1067-
; This could be resolved in the future with more detailed KnownBits analysis
1068-
; for ISD::VSCALE.
1069-
1070-
define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) {
1071-
; RV32-LABEL: vmax_vx_nxv32i32_evl_nx16:
1072-
; RV32: # %bb.0:
1073-
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1074-
; RV32-NEXT: vmax.vx v8, v8, a0, v0.t
1075-
; RV32-NEXT: ret
1076-
;
1077-
; RV64-LABEL: vmax_vx_nxv32i32_evl_nx16:
1078-
; RV64: # %bb.0:
1079-
; RV64-NEXT: csrr a1, vlenb
1080-
; RV64-NEXT: srli a1, a1, 2
1081-
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
1082-
; RV64-NEXT: vslidedown.vx v24, v0, a1
1083-
; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1084-
; RV64-NEXT: vmax.vx v8, v8, a0, v0.t
1085-
; RV64-NEXT: vmv1r.v v0, v24
1086-
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma
1087-
; RV64-NEXT: vmax.vx v16, v16, a0, v0.t
1088-
; RV64-NEXT: ret
1063+
; The attribute vscale_range(2,1024) given here can remove the zero_extend for
1064+
; the i32 %evl to i64 on RV64 through KnownBits analysis.
1065+
1066+
define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) vscale_range(2,1024) {
1067+
; CHECK-LABEL: vmax_vx_nxv32i32_evl_nx16:
1068+
; CHECK: # %bb.0:
1069+
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1070+
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
1071+
; CHECK-NEXT: ret
10891072
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
10901073
%vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer
10911074
%evl = call i32 @llvm.vscale.i32()

‎llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll‎

Lines changed: 9 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1059,32 +1059,15 @@ define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
10591059
ret <vscale x 32 x i32> %v
10601060
}
10611061

1062-
; FIXME: The upper half of the operation is doing nothing but we don't catch
1063-
; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16)
1064-
; (the "original" %evl is the "and", due to known-bits issues with legalizing
1065-
; the i32 %evl to i64) and this isn't detected as 0.
1066-
; This could be resolved in the future with more detailed KnownBits analysis
1067-
; for ISD::VSCALE.
1068-
1069-
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) {
1070-
; RV32-LABEL: vmaxu_vx_nxv32i32_evl_nx16:
1071-
; RV32: # %bb.0:
1072-
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1073-
; RV32-NEXT: vmaxu.vx v8, v8, a0, v0.t
1074-
; RV32-NEXT: ret
1075-
;
1076-
; RV64-LABEL: vmaxu_vx_nxv32i32_evl_nx16:
1077-
; RV64: # %bb.0:
1078-
; RV64-NEXT: csrr a1, vlenb
1079-
; RV64-NEXT: srli a1, a1, 2
1080-
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
1081-
; RV64-NEXT: vslidedown.vx v24, v0, a1
1082-
; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1083-
; RV64-NEXT: vmaxu.vx v8, v8, a0, v0.t
1084-
; RV64-NEXT: vmv1r.v v0, v24
1085-
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma
1086-
; RV64-NEXT: vmaxu.vx v16, v16, a0, v0.t
1087-
; RV64-NEXT: ret
1062+
; The attribute vscale_range(2,1024) given here can remove the zero_extend for
1063+
; the i32 %evl to i64 on RV64 through KnownBits analysis.
1064+
1065+
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) vscale_range(2,1024) {
1066+
; CHECK-LABEL: vmaxu_vx_nxv32i32_evl_nx16:
1067+
; CHECK: # %bb.0:
1068+
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1069+
; CHECK-NEXT: vmaxu.vx v8, v8, a0, v0.t
1070+
; CHECK-NEXT: ret
10881071
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
10891072
%vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer
10901073
%evl = call i32 @llvm.vscale.i32()

‎llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll‎

Lines changed: 9 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,32 +1060,15 @@ define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
10601060
ret <vscale x 32 x i32> %v
10611061
}
10621062

1063-
; FIXME: The upper half of the operation is doing nothing but we don't catch
1064-
; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16)
1065-
; (the "original" %evl is the "and", due to known-bits issues with legalizing
1066-
; the i32 %evl to i64) and this isn't detected as 0.
1067-
; This could be resolved in the future with more detailed KnownBits analysis
1068-
; for ISD::VSCALE.
1069-
1070-
define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) {
1071-
; RV32-LABEL: vmin_vx_nxv32i32_evl_nx16:
1072-
; RV32: # %bb.0:
1073-
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1074-
; RV32-NEXT: vmin.vx v8, v8, a0, v0.t
1075-
; RV32-NEXT: ret
1076-
;
1077-
; RV64-LABEL: vmin_vx_nxv32i32_evl_nx16:
1078-
; RV64: # %bb.0:
1079-
; RV64-NEXT: csrr a1, vlenb
1080-
; RV64-NEXT: srli a1, a1, 2
1081-
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
1082-
; RV64-NEXT: vslidedown.vx v24, v0, a1
1083-
; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1084-
; RV64-NEXT: vmin.vx v8, v8, a0, v0.t
1085-
; RV64-NEXT: vmv1r.v v0, v24
1086-
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma
1087-
; RV64-NEXT: vmin.vx v16, v16, a0, v0.t
1088-
; RV64-NEXT: ret
1063+
; The attribute vscale_range(2,1024) given here can remove the zero_extend for
1064+
; the i32 %evl to i64 on RV64 through KnownBits analysis.
1065+
1066+
define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) vscale_range(2,1024) {
1067+
; CHECK-LABEL: vmin_vx_nxv32i32_evl_nx16:
1068+
; CHECK: # %bb.0:
1069+
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1070+
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
1071+
; CHECK-NEXT: ret
10891072
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
10901073
%vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer
10911074
%evl = call i32 @llvm.vscale.i32()

‎llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll‎

Lines changed: 9 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1059,32 +1059,15 @@ define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
10591059
ret <vscale x 32 x i32> %v
10601060
}
10611061

1062-
; FIXME: The upper half of the operation is doing nothing but we don't catch
1063-
; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16)
1064-
; (the "original" %evl is the "and", due to known-bits issues with legalizing
1065-
; the i32 %evl to i64) and this isn't detected as 0.
1066-
; This could be resolved in the future with more detailed KnownBits analysis
1067-
; for ISD::VSCALE.
1068-
1069-
define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) {
1070-
; RV32-LABEL: vminu_vx_nxv32i32_evl_nx16:
1071-
; RV32: # %bb.0:
1072-
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1073-
; RV32-NEXT: vminu.vx v8, v8, a0, v0.t
1074-
; RV32-NEXT: ret
1075-
;
1076-
; RV64-LABEL: vminu_vx_nxv32i32_evl_nx16:
1077-
; RV64: # %bb.0:
1078-
; RV64-NEXT: csrr a1, vlenb
1079-
; RV64-NEXT: srli a1, a1, 2
1080-
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
1081-
; RV64-NEXT: vslidedown.vx v24, v0, a1
1082-
; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1083-
; RV64-NEXT: vminu.vx v8, v8, a0, v0.t
1084-
; RV64-NEXT: vmv1r.v v0, v24
1085-
; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma
1086-
; RV64-NEXT: vminu.vx v16, v16, a0, v0.t
1087-
; RV64-NEXT: ret
1062+
; The attribute vscale_range(2,1024) given here can remove the zero_extend for
1063+
; the i32 %evl to i64 on RV64 through KnownBits analysis.
1064+
1065+
define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) vscale_range(2,1024) {
1066+
; CHECK-LABEL: vminu_vx_nxv32i32_evl_nx16:
1067+
; CHECK: # %bb.0:
1068+
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1069+
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
1070+
; CHECK-NEXT: ret
10881071
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
10891072
%vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer
10901073
%evl = call i32 @llvm.vscale.i32()

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