Skip to content

Commit 9930e22

Browse files
bjornspockcarlescufi
bjornspock
authored and
carlescufi
committed
Bluetooth: controller: Add GPIO control for nRF21540 CSN and PDN lines
Added GPIO control for nRF21540 CSN and PDN lines. Signed-off-by: Bjørn Spockeli <[email protected]> Signed-off-by: Vinayak Kariappa Chettimada <[email protected]>
1 parent 568113c commit 9930e22

File tree

4 files changed

+242
-5
lines changed

4 files changed

+242
-5
lines changed

‎subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c‎

Lines changed: 123 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,27 @@
4141
#endif
4242
#endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */
4343

44+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
45+
#if ((CONFIG_BT_CTLR_GPIO_PDN_PIN) > 31)
46+
#define NRF_GPIO_PDN NRF_P1
47+
#define NRF_GPIO_PDN_PIN ((CONFIG_BT_CTLR_GPIO_PDN_PIN) - 32)
48+
#else
49+
#define NRF_GPIO_PDN NRF_P0
50+
#define NRF_GPIO_PDN_PIN CONFIG_BT_CTLR_GPIO_PDN_PIN
51+
#endif
52+
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */
53+
54+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
55+
#if ((CONFIG_BT_CTLR_GPIO_CSN_PIN) > 31)
56+
#define NRF_GPIO_CSN NRF_P1
57+
#define NRF_GPIO_CSN_PIN ((CONFIG_BT_CTLR_GPIO_CSN_PIN) - 32)
58+
#else
59+
#define NRF_GPIO_CSN NRF_P0
60+
#define NRF_GPIO_CSN_PIN CONFIG_BT_CTLR_GPIO_CSN_PIN
61+
#endif
62+
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */
63+
64+
4465
/* The following two constants are used in nrfx_glue.h for marking these PPI
4566
* channels and groups as occupied and thus unavailable to other modules.
4667
*/
@@ -97,6 +118,24 @@ void radio_setup(void)
97118
radio_gpio_lna_off();
98119
#endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */
99120

121+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
122+
NRF_GPIO_PDN->DIRSET = BIT(NRF_GPIO_PDN_PIN);
123+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
124+
NRF_GPIO_PDN->OUTSET = BIT(NRF_GPIO_PDN_PIN);
125+
#else
126+
NRF_GPIO_PDN->OUTCLR = BIT(NRF_GPIO_PDN_PIN);
127+
#endif
128+
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */
129+
130+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
131+
NRF_GPIO_CSN->DIRSET = BIT(NRF_GPIO_CSN_PIN);
132+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
133+
NRF_GPIO_CSN->OUTSET = BIT(NRF_GPIO_CSN_PIN);
134+
#else
135+
NRF_GPIO_CSN->OUTCLR = BIT(NRF_GPIO_CSN_PIN);
136+
#endif
137+
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */
138+
100139
hal_radio_ram_prio_setup();
101140
}
102141

@@ -122,6 +161,9 @@ void radio_reset(void)
122161
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
123162
hal_palna_ppi_setup();
124163
#endif
164+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
165+
hal_fem_ppi_setup();
166+
#endif
125167
}
126168

127169
void radio_phy_set(uint8_t phy, uint8_t flags)
@@ -982,6 +1024,12 @@ void radio_gpio_pa_setup(void)
9821024
(GPIOTE_CONFIG_OUTINIT_Low <<
9831025
GPIOTE_CONFIG_OUTINIT_Pos);
9841026
#endif
1027+
1028+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
1029+
hal_pa_ppi_setup();
1030+
radio_gpio_pdn_setup();
1031+
radio_gpio_csn_setup();
1032+
#endif
9851033
}
9861034
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN */
9871035

@@ -1006,8 +1054,62 @@ void radio_gpio_lna_setup(void)
10061054
(GPIOTE_CONFIG_OUTINIT_Low <<
10071055
GPIOTE_CONFIG_OUTINIT_Pos);
10081056
#endif
1057+
1058+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
1059+
hal_lna_ppi_setup();
1060+
radio_gpio_pdn_setup();
1061+
radio_gpio_csn_setup();
1062+
#endif
10091063
}
10101064

1065+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
1066+
void radio_gpio_pdn_setup(void)
1067+
{
1068+
/* NOTE: With GPIO Pins above 31, left shift of
1069+
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
1070+
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
1071+
*/
1072+
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] =
1073+
(GPIOTE_CONFIG_MODE_Task <<
1074+
GPIOTE_CONFIG_MODE_Pos) |
1075+
(CONFIG_BT_CTLR_GPIO_PDN_PIN <<
1076+
GPIOTE_CONFIG_PSEL_Pos) |
1077+
(GPIOTE_CONFIG_POLARITY_Toggle <<
1078+
GPIOTE_CONFIG_POLARITY_Pos) |
1079+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
1080+
(GPIOTE_CONFIG_OUTINIT_High <<
1081+
GPIOTE_CONFIG_OUTINIT_Pos);
1082+
#else
1083+
(GPIOTE_CONFIG_OUTINIT_Low <<
1084+
GPIOTE_CONFIG_OUTINIT_Pos);
1085+
#endif
1086+
}
1087+
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */
1088+
1089+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
1090+
void radio_gpio_csn_setup(void)
1091+
{
1092+
/* NOTE: With GPIO Pins above 31, left shift of
1093+
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
1094+
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
1095+
*/
1096+
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] =
1097+
(GPIOTE_CONFIG_MODE_Task <<
1098+
GPIOTE_CONFIG_MODE_Pos) |
1099+
(CONFIG_BT_CTLR_GPIO_CSN_PIN <<
1100+
GPIOTE_CONFIG_PSEL_Pos) |
1101+
(GPIOTE_CONFIG_POLARITY_Toggle <<
1102+
GPIOTE_CONFIG_POLARITY_Pos) |
1103+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
1104+
(GPIOTE_CONFIG_OUTINIT_High <<
1105+
GPIOTE_CONFIG_OUTINIT_Pos);
1106+
#else
1107+
(GPIOTE_CONFIG_OUTINIT_Low <<
1108+
GPIOTE_CONFIG_OUTINIT_Pos);
1109+
#endif
1110+
}
1111+
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */
1112+
10111113
void radio_gpio_lna_on(void)
10121114
{
10131115
#if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV)
@@ -1030,15 +1132,34 @@ void radio_gpio_lna_off(void)
10301132
void radio_gpio_pa_lna_enable(uint32_t trx_us)
10311133
{
10321134
nrf_timer_cc_set(EVENT_TIMER, 2, trx_us);
1135+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
1136+
nrf_timer_cc_set(EVENT_TIMER, 3, (trx_us -
1137+
CONFIG_BT_CTLR_GPIO_PDN_CSN_OFFSET));
10331138
hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1034-
BIT(HAL_DISABLE_PALNA_PPI));
1139+
BIT(HAL_DISABLE_PALNA_PPI) |
1140+
BIT(HAL_ENABLE_FEM_PPI) |
1141+
BIT(HAL_DISABLE_FEM_PPI));
1142+
#else
1143+
hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1144+
BIT(HAL_DISABLE_PALNA_PPI));
1145+
#endif
10351146
}
10361147

10371148
void radio_gpio_pa_lna_disable(void)
10381149
{
1150+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
10391151
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1040-
BIT(HAL_DISABLE_PALNA_PPI));
1152+
BIT(HAL_DISABLE_PALNA_PPI) |
1153+
BIT(HAL_ENABLE_FEM_PPI) |
1154+
BIT(HAL_DISABLE_FEM_PPI));
10411155
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
1156+
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] = 0;
1157+
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] = 0;
1158+
#else
1159+
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1160+
BIT(HAL_DISABLE_PALNA_PPI));
1161+
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
1162+
#endif
10421163
}
10431164
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
10441165

‎subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,8 @@ uint32_t radio_tmr_sample_get(void);
8888

8989
void radio_gpio_pa_setup(void);
9090
void radio_gpio_lna_setup(void);
91+
void radio_gpio_pdn_setup(void);
92+
void radio_gpio_csn_setup(void);
9193
void radio_gpio_lna_on(void);
9294
void radio_gpio_lna_off(void);
9395
void radio_gpio_pa_lna_enable(uint32_t trx_us);

‎subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h‎

Lines changed: 95 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,23 +173,106 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
173173
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
174174

175175
#define HAL_ENABLE_PALNA_PPI 5
176+
177+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
178+
#define HAL_DISABLE_PALNA_PPI 4
179+
#else
176180
#define HAL_DISABLE_PALNA_PPI HAL_ENABLE_PALNA_PPI
181+
#endif
177182

178183
static inline void hal_palna_ppi_setup(void)
179184
{
180-
nrf_gpiote_task_t task;
181-
182185
nrf_timer_publish_set(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE2,
183186
HAL_ENABLE_PALNA_PPI);
184187
nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_DISABLED,
185188
HAL_DISABLE_PALNA_PPI);
186189

190+
#if !defined(CONFIG_BT_CTLR_FEM_NRF21540)
191+
nrf_gpiote_task_t task;
192+
187193
task = nrf_gpiote_out_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
188194
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
195+
#endif
189196
}
190197

191198
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
192199

200+
/******************************************************************************/
201+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
202+
203+
static inline void hal_pa_ppi_setup(void)
204+
{
205+
nrf_gpiote_task_t task;
206+
207+
#if defined(CONFIG_BT_CTLR_GPIO_PA_POL_INV)
208+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
209+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
210+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
211+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
212+
#else /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
213+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
214+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
215+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
216+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
217+
#endif /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
218+
}
219+
220+
static inline void hal_lna_ppi_setup(void)
221+
{
222+
nrf_gpiote_task_t task;
223+
224+
#if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV)
225+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
226+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
227+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
228+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
229+
#else /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
230+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
231+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
232+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
233+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
234+
#endif /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
235+
}
236+
237+
#define HAL_ENABLE_FEM_PPI 3
238+
#define HAL_DISABLE_FEM_PPI HAL_DISABLE_PALNA_PPI
239+
240+
static inline void hal_fem_ppi_setup(void)
241+
{
242+
nrf_gpiote_task_t task;
243+
244+
nrf_timer_publish_set(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE3,
245+
HAL_ENABLE_FEM_PPI);
246+
nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_DISABLED,
247+
HAL_DISABLE_FEM_PPI);
248+
249+
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
250+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
251+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
252+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
253+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
254+
#else /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
255+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
256+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
257+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
258+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
259+
#endif /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
260+
261+
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
262+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
263+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
264+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
265+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
266+
#else /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
267+
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
268+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
269+
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
270+
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
271+
#endif /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
272+
}
273+
274+
#endif /* CONFIG_BT_CTLR_FEM_NRF21540 */
275+
193276
/******************************************************************************/
194277
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
195278
/* DPPI setup used for SW-based auto-switching during TIFS. */
@@ -547,7 +630,8 @@ static inline void hal_radio_group_task_disable_ppi_setup(void)
547630
BIT(HAL_TRIGGER_CRYPT_PPI) | \
548631
BIT(HAL_TRIGGER_AAR_PPI) | \
549632
HAL_USED_PPI_CHANNELS_2 | HAL_USED_PPI_CHANNELS_3 | \
550-
HAL_USED_PPI_CHANNELS_4 | HAL_USED_PPI_CHANNELS_5)
633+
HAL_USED_PPI_CHANNELS_4 | HAL_USED_PPI_CHANNELS_5 | \
634+
HAL_USED_PPI_CHANNELS_6)
551635

552636
#if defined(HAL_TRIGGER_RATEOVERRIDE_PPI)
553637
#define HAL_USED_PPI_CHANNELS_2 \
@@ -585,6 +669,14 @@ static inline void hal_radio_group_task_disable_ppi_setup(void)
585669
#define HAL_USED_PPI_CHANNELS_5 0
586670
#endif
587671

672+
#if defined(HAL_ENABLE_FEM_PPI)
673+
#define HAL_USED_PPI_CHANNELS_6 \
674+
(BIT(HAL_ENABLE_FEM_PPI) | \
675+
BIT(HAL_DISABLE_FEM_PPI))
676+
#else
677+
#define HAL_USED_PPI_CHANNELS_6 0
678+
#endif
679+
588680
BUILD_ASSERT(
589681
(HAL_USED_PPI_CHANNELS & NRFX_PPI_CHANNELS_USED_BY_PWM_SW) == 0,
590682
"PPI channels used by the Bluetooth controller overlap with those "

‎subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -285,6 +285,28 @@ static inline void hal_palna_ppi_setup(void)
285285

286286
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
287287

288+
/******************************************************************************/
289+
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
290+
static inline void hal_pa_ppi_setup(void)
291+
{
292+
/* Nothing specific to PA with FEM to handle inside TRX chains */
293+
}
294+
295+
static inline void hal_lna_ppi_setup(void)
296+
{
297+
/* Nothing specific to LNA with FEM to handle inside TRX chains */
298+
}
299+
300+
/* TODO: Dummy assignments, implementation will be added in subsequently */
301+
#define HAL_ENABLE_FEM_PPI 4
302+
#define HAL_DISABLE_FEM_PPI 5
303+
304+
static inline void hal_fem_ppi_setup(void)
305+
{
306+
/* TODO: Implementation will be added in subsequently */
307+
}
308+
#endif /* CONFIG_BT_CTLR_FEM_NRF21540 */
309+
288310
/******************************************************************************/
289311
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
290312
/* PPI setup used for SW-based auto-switching during TIFS. */

0 commit comments

Comments
 (0)