cavs: fix LSPGISTS and LSPGCTL access

On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.

Signed-off-by: Guennadi Liakhovetski <[email protected]>

Author: lyakh

soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h

@@ -204,6 +204,7 @@
 #define SHIM_HSPGCTL		0x80
 #define SHIM_LSPGCTL		0x84
 #define SHIM_SPSREQ		0xa0
+#define LSPGCTL			(SHIM_BASE + SHIM_LSPGCTL)
 
 #define SHIM_SPSREQ_RVNNP	BIT(0)
 

soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h

@@ -236,10 +236,6 @@
 #define LSRMCTL			0x71D54
 #define LSPGISTS		0x71D58
 
-#define SHIM_LSPGCTL		0x50
-#define SHIM_LSPGISTS		0x58
-
-
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */

soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h

@@ -230,10 +230,6 @@
 #define LSRMCTL			0x71D54
 #define LSPGISTS		0x71D58
 
-#define SHIM_LSPGCTL		0x50
-#define SHIM_LSPGISTS		0x58
-
-
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */

soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h

@@ -239,10 +239,6 @@
 #define LSRMCTL			0x71D54
 #define LSPGISTS		0x71D58
 
-#define SHIM_LSPGCTL		0x50
-#define SHIM_LSPGISTS		0x58
-
-
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */

soc/xtensa/intel_adsp/common/bootloader/boot_loader.c

@@ -301,8 +301,8 @@ static int32_t lp_sram_init(void)
 	/* add some delay before writing power registers */
 	idelay(delay_count);
 
-	lspgctl_value = shim_read(SHIM_LSPGISTS);
-	shim_write(SHIM_LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0));
+	lspgctl_value = io_reg_read(LSPGISTS);
+	io_reg_write(LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0));
 
 	/* add some delay before checking the status */
 	idelay(delay_count);