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Merge branch 'netwide-assembler:master' into master
2 parents e3820fd + 94923e1 commit 258e7d1

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-315
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‎.gitignore‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
*.ith
1515
*.lib
1616
*.lst
17+
*.log
1718
*.map
1819
*.mo32
1920
*.mo64
@@ -122,3 +123,4 @@ TAGS
122123
/autoconf/config.*
123124
/autoconf/install-sh
124125
/autoconf/clean.sh
126+
/travis/test/_version.stdout

‎Makefile.in‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,7 @@ ZLIBOBJ = \
224224

225225
LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB)
226226
ALLOBJ_W = $(NASM) $(LIBOBJ_W)
227-
ALLOBJ = $(PROGOBJ) $(LIBOBJ)
227+
ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS)
228228
SUBDIRS = stdlib nasmlib include config output asm disasm x86 \
229229
common zlib macros misc
230230
XSUBDIRS = nsis win test doc editors
@@ -262,7 +262,7 @@ ndisasm$(X): $(NDISASM) $(MANIFEST) $(DISLIB) $(NASMLIB)
262262
$(DISLIB) $(NASMLIB) $(LIBS)
263263

264264
# Make sure we have subdirectories set up...
265-
$(LIBOBJ) $(LIBOBJ_DIS): $(DIRS)
265+
$(ALLOBJ): $(DIRS)
266266

267267
#-- Begin Generated File Rules --#
268268

‎Mkfiles/msvc.mak‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,7 @@ ZLIBOBJ = \
175175

176176
LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB)
177177
ALLOBJ_W = $(NASM) $(LIBOBJ_W)
178-
ALLOBJ = $(PROGOBJ) $(LIBOBJ)
178+
ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS)
179179
SUBDIRS = stdlib nasmlib include config output asm disasm x86 \
180180
common zlib macros misc
181181
XSUBDIRS = nsis win test doc editors

‎Mkfiles/openwcom.mak‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ ZLIBOBJ = &
161161

162162
LIBOBJ = $(LIBOBJ_W) $(LIBOBJ_NW) $(ZLIB)
163163
ALLOBJ_W = $(NASM) $(LIBOBJ_W)
164-
ALLOBJ = $(PROGOBJ) $(LIBOBJ)
164+
ALLOBJ = $(PROGOBJ) $(LIBOBJ) $(LIBOBJ_DIS)
165165
SUBDIRS = stdlib nasmlib include config output asm disasm x86 &
166166
common zlib macros misc
167167
XSUBDIRS = nsis win test doc editors
@@ -404,6 +404,7 @@ clean: .SYMBOLIC
404404
rm -f stdlib\*.obj stdlib\*.s stdlib\*.i
405405
rm -f nasmlib\*.obj nasmlib\*.s nasmlib\*.i
406406
rm -f disasm\*.obj disasm\*.s disasm\*.i
407+
rm -f zlib\*.obj zlib\*.s zlib\*.i
407408
rm -f config.h config.log config.status
408409
rm -f nasm$(X) ndisasm$(X) $(NASMLIB) $(NDISLIB)
409410

‎asm/assemble.c‎

Lines changed: 83 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -634,6 +634,82 @@ static void out_reladdr(struct out_data *data, const struct operand *opx,
634634
out(data);
635635
}
636636

637+
/* Issue an error message on match failure */
638+
static void no_match_error(enum match_result m, const insn *ins)
639+
{
640+
/* No match */
641+
switch (m) {
642+
case MERR_INVALOP:
643+
nasm_holderr("invalid combination of opcode and operands");
644+
break;
645+
case MERR_OPSIZEINVAL:
646+
nasm_holderr("invalid operand sizes for instruction");
647+
break;
648+
case MERR_OPSIZEMISSING:
649+
nasm_holderr("operation size not specified");
650+
break;
651+
case MERR_OPSIZEMISMATCH:
652+
nasm_holderr("mismatch in operand sizes");
653+
break;
654+
case MERR_BRNOTHERE:
655+
nasm_holderr("broadcast not permitted on this operand");
656+
break;
657+
case MERR_BRNUMMISMATCH:
658+
nasm_holderr("mismatch in the number of broadcasting elements");
659+
break;
660+
case MERR_MASKNOTHERE:
661+
nasm_holderr("mask not permitted on this operand");
662+
break;
663+
case MERR_DECONOTHERE:
664+
nasm_holderr("unsupported mode decorator for instruction");
665+
break;
666+
case MERR_BADCPU:
667+
nasm_holderr("no instruction for this cpu level");
668+
break;
669+
case MERR_BADMODE:
670+
nasm_holderr("instruction not supported in %d-bit mode", ins->bits);
671+
break;
672+
case MERR_ENCMISMATCH:
673+
if (!ins->prefixes[PPS_REX]) {
674+
nasm_holderr("instruction not encodable without explicit prefix");
675+
} else {
676+
nasm_holderr("instruction not encodable with %s prefix",
677+
prefix_name(ins->prefixes[PPS_REX]));
678+
}
679+
break;
680+
case MERR_BADBND:
681+
case MERR_BADREPNE:
682+
nasm_holderr("%s prefix is not allowed",
683+
prefix_name(ins->prefixes[PPS_REP]));
684+
break;
685+
case MERR_REGSETSIZE:
686+
nasm_holderr("invalid register set size");
687+
break;
688+
case MERR_REGSET:
689+
nasm_holderr("register set not valid for operand");
690+
break;
691+
case MERR_WRONGIMM:
692+
nasm_holderr("operand/operator invalid for this instruction");
693+
break;
694+
case MERR_BADZU:
695+
nasm_holderr("{zu} not applicable to this instruction");
696+
break;
697+
case MERR_MEMZU:
698+
nasm_holderr("{zu} invalid for non-register destination");
699+
break;
700+
case MERR_BADNF:
701+
nasm_holderr("{nf} not available for this instruction");
702+
break;
703+
case MERR_REQNF:
704+
nasm_holderr("{nf} required for this instruction");
705+
break;
706+
default:
707+
if (m < MOK_GOOD)
708+
nasm_holderr("invalid use of instruction");
709+
break;
710+
}
711+
}
712+
637713
/* This is a real hack. The jcc8 or jmp8 byte code must come first. */
638714
static enum match_result jmp_match(const struct itemplate *temp, const insn *ins)
639715
{
@@ -816,7 +892,6 @@ static int64_t assemble(insn *instruction)
816892
const struct itemplate *temp;
817893
enum match_result m;
818894
const int64_t start = instruction->loc.offset;
819-
const int bits = instruction->bits;
820895

821896
if (instruction->opcode == I_none)
822897
return 0;
@@ -999,75 +1074,7 @@ static int64_t assemble(insn *instruction)
9991074

10001075
nasm_assert(data.loc.offset - start == data.inslen);
10011076
} else {
1002-
/* No match */
1003-
switch (m) {
1004-
case MERR_INVALOP:
1005-
default:
1006-
nasm_nonfatal("invalid combination of opcode and operands");
1007-
break;
1008-
case MERR_OPSIZEINVAL:
1009-
nasm_nonfatal("invalid operand sizes for instruction");
1010-
break;
1011-
case MERR_OPSIZEMISSING:
1012-
nasm_nonfatal("operation size not specified");
1013-
break;
1014-
case MERR_OPSIZEMISMATCH:
1015-
nasm_nonfatal("mismatch in operand sizes");
1016-
break;
1017-
case MERR_BRNOTHERE:
1018-
nasm_nonfatal("broadcast not permitted on this operand");
1019-
break;
1020-
case MERR_BRNUMMISMATCH:
1021-
nasm_nonfatal("mismatch in the number of broadcasting elements");
1022-
break;
1023-
case MERR_MASKNOTHERE:
1024-
nasm_nonfatal("mask not permitted on this operand");
1025-
break;
1026-
case MERR_DECONOTHERE:
1027-
nasm_nonfatal("unsupported mode decorator for instruction");
1028-
break;
1029-
case MERR_BADCPU:
1030-
nasm_nonfatal("no instruction for this cpu level");
1031-
break;
1032-
case MERR_BADMODE:
1033-
nasm_nonfatal("instruction not supported in %d-bit mode", bits);
1034-
break;
1035-
case MERR_ENCMISMATCH:
1036-
if (!instruction->prefixes[PPS_REX]) {
1037-
nasm_nonfatal("instruction not encodable without explicit prefix");
1038-
} else {
1039-
nasm_nonfatal("instruction not encodable with %s prefix",
1040-
prefix_name(instruction->prefixes[PPS_REX]));
1041-
}
1042-
break;
1043-
case MERR_BADBND:
1044-
case MERR_BADREPNE:
1045-
nasm_nonfatal("%s prefix is not allowed",
1046-
prefix_name(instruction->prefixes[PPS_REP]));
1047-
break;
1048-
case MERR_REGSETSIZE:
1049-
nasm_nonfatal("invalid register set size");
1050-
break;
1051-
case MERR_REGSET:
1052-
nasm_nonfatal("register set not valid for operand");
1053-
break;
1054-
case MERR_WRONGIMM:
1055-
nasm_nonfatal("operand/operator invalid for this instruction");
1056-
break;
1057-
case MERR_BADZU:
1058-
nasm_nonfatal("{zu} not applicable to this instruction");
1059-
break;
1060-
case MERR_MEMZU:
1061-
nasm_nonfatal("{zu} invalid for non-register destination");
1062-
break;
1063-
case MERR_BADNF:
1064-
nasm_nonfatal("{nf} not available for this instruction");
1065-
break;
1066-
case MERR_REQNF:
1067-
nasm_nonfatal("{nf} required for this instruction");
1068-
break;
1069-
}
1070-
1077+
no_match_error(m, instruction);
10711078
instruction->times = 1; /* Avoid repeated error messages */
10721079
}
10731080
}
@@ -1285,8 +1292,10 @@ static int64_t insn_size(insn *instruction)
12851292
insn_early_setup(instruction);
12861293

12871294
m = find_match(&temp, instruction);
1288-
if (m < MOK_GOOD)
1295+
if (m < MOK_GOOD) {
1296+
no_match_error(m, instruction);
12891297
return -1; /* No match */
1298+
}
12901299

12911300
isize = calcsize(instruction, temp);
12921301
debug_set_type(instruction);
@@ -3107,24 +3116,10 @@ static enum match_result matches(const struct itemplate * const itemp,
31073116
/*
31083117
* If this is an *explicitly* sized immediate,
31093118
* allow it to match an extending pattern.
3119+
*
3120+
* NOTE: Open Watcom does not support 64-bit constants
3121+
* in switch statements; do not change this to a switch.
31103122
*/
3111-
#ifndef __WATCOMC__
3112-
switch (isize[i]) {
3113-
case BITS8:
3114-
if (ttype & BYTEEXTMASK) {
3115-
isize[i] = tsize[i];
3116-
itype[i] |= BYTEEXTMASK;
3117-
}
3118-
break;
3119-
case BITS32:
3120-
if (ttype & DWORDEXTMASK)
3121-
isize[i] = tsize[i];
3122-
break;
3123-
default:
3124-
break;
3125-
}
3126-
#else
3127-
/* Open Watcom does not support 64-bit constants at *case*. */
31283123
if (isize[i] == BITS8) {
31293124
if (ttype & BYTEEXTMASK) {
31303125
isize[i] = tsize[i];
@@ -3134,7 +3129,6 @@ static enum match_result matches(const struct itemplate * const itemp,
31343129
if (ttype & DWORDEXTMASK)
31353130
isize[i] = tsize[i];
31363131
}
3137-
#endif
31383132

31393133
/*
31403134
* MOST instructions which take an sdword64 are the only form;

‎asm/error.c‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,17 +13,21 @@ unsigned int debug_nasm; /* Debugging messages? */
1313
unsigned int opt_verbose_info; /* Informational messages? */
1414

1515
/* Common function body */
16-
#define nasm_do_error(_sev,_flags) \
16+
#define nasm_do_error(_sev,_flags) \
1717
do { \
18+
const errflags nde_severity = (_sev); \
19+
const errflags nde_flags = nde_severity | (_flags); \
1820
va_list ap; \
1921
va_start(ap, fmt); \
20-
if ((_sev) >= ERR_CRITICAL) \
21-
nasm_verror_critical((_sev)|(_flags), fmt, ap); \
22-
else \
23-
nasm_verror((_sev)|(_flags), fmt, ap); \
22+
if (nde_severity >= ERR_CRITICAL) { \
23+
nasm_verror_critical(nde_flags, fmt, ap); \
24+
unreachable(); \
25+
} else { \
26+
nasm_verror(nde_flags, fmt, ap); \
27+
if (nde_severity >= ERR_FATAL) \
28+
unreachable(); \
29+
} \
2430
va_end(ap); \
25-
if ((_sev) >= ERR_FATAL) \
26-
abort(); \
2731
} while (0)
2832

2933
/*
@@ -81,6 +85,14 @@ void nasm_debug_(unsigned int level, const char *fmt, ...)
8185
nasm_do_error(ERR_DEBUG, LEVEL(level));
8286
}
8387

88+
/*
89+
* Convenience function for nasm_nonfatal(ERR_HOLD, ...)
90+
*/
91+
void nasm_holderr(const char *fmt, ...)
92+
{
93+
nasm_do_error(ERR_NONFATAL, ERR_NONFATAL|ERR_HOLD);
94+
}
95+
8496
fatal_func nasm_panic_from_macro(const char *func, const char *file, int line)
8597
{
8698
if (!func)

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