Skip to content

Commit 9f31c84

Browse files
author
H. Peter Anvin
committed
insns: handle late-introduced VEX encoded instructions
For VEX instructions created *after* the corresponding EVEX instructions, we need the user to either explicitly declare them {vex} or specifying "cpu latevex". Signed-off-by: H. Peter Anvin <[email protected]>
1 parent d3afc5c commit 9f31c84

File tree

8 files changed

+150
-81
lines changed

8 files changed

+150
-81
lines changed

‎asm/assemble.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2552,6 +2552,10 @@ static enum match_result matches(const struct itemplate *itemp,
25522552
return MERR_ENCMISMATCH;
25532553
break;
25542554
default:
2555+
if (itemp_has(itemp, IF_LATEVEX)) {
2556+
if (!iflag_test(&cpu, IF_LATEVEX))
2557+
return MERR_ENCMISMATCH;
2558+
}
25552559
break;
25562560
}
25572561

‎asm/assemble.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,9 @@
4141
#include "nasm.h"
4242
#include "iflag.h"
4343

44-
extern iflag_t cpu;
44+
extern iflag_t cpu, cmd_cpu;
45+
void set_cpu(const char *cpuspec);
46+
4547
extern bool in_absolute; /* Are we in an absolute segment? */
4648
extern struct location absolute;
4749

‎asm/directiv.c

Lines changed: 79 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* ----------------------------------------------------------------------- *
22
*
3-
* Copyright 1996-2019 The NASM Authors - All Rights Reserved
3+
* Copyright 1996-2022 The NASM Authors - All Rights Reserved
44
* See the file AUTHORS included with the NASM distribution for
55
* the specific copyright holders.
66
*
@@ -59,11 +59,25 @@ struct cpunames {
5959
/* Eventually a table of features */
6060
};
6161

62-
static iflag_t get_cpu(const char *value)
62+
static void iflag_set_cpu(iflag_t *a, unsigned int lvl)
6363
{
64-
iflag_t r;
65-
const struct cpunames *cpu;
64+
a->field[0] = 0; /* Not applicable to the CPU type */
65+
iflag_set_all_features(a); /* All feature masking bits set for now */
66+
if (lvl >= IF_ANY) {
67+
/* This is a hack for now */
68+
iflag_set(a, IF_LATEVEX);
69+
}
70+
a->field[IF_CPU_FIELD] &= ~IF_CPU_LEVEL_MASK;
71+
iflag_set(a, lvl);
72+
}
73+
74+
void set_cpu(const char *value)
75+
{
76+
const char *p;
77+
char modifier;
78+
const struct cpunames *cpuflag;
6679
static const struct cpunames cpunames[] = {
80+
{ "default", IF_DEFAULT }, /* Must be first */
6781
{ "8086", IF_8086 },
6882
{ "186", IF_186 },
6983
{ "286", IF_286 },
@@ -96,22 +110,69 @@ static iflag_t get_cpu(const char *value)
96110
{ "ivybridge", IF_FUTURE },
97111
{ "any", IF_ANY },
98112
{ "all", IF_ANY },
99-
{ "default", IF_PLEVEL },
100-
{ NULL, IF_PLEVEL } /* Error and final default entry */
113+
{ "latevex", IF_LATEVEX },
114+
{ NULL, IF_DEFAULT } /* End of list */
101115
};
102116

103-
iflag_clear_all(&r);
104-
105-
for (cpu = cpunames; cpu->name; cpu++) {
106-
if (!nasm_stricmp(value, cpu->name))
107-
break;
117+
if (!value) {
118+
iflag_set_cpu(&cpu, cpunames[0].level);
119+
return;
108120
}
109121

110-
if (!cpu->name)
111-
nasm_nonfatal("unknown 'cpu' type '%s'", value);
122+
p = value;
123+
modifier = '+';
124+
while (*p) {
125+
int len = strcspn(p, " ,");
126+
127+
while (len && (*p == '+' || *p == '-' || *p == '*')) {
128+
modifier = *p++;
129+
len--;
130+
if (!len && modifier == '*')
131+
cpu = cmd_cpu;
132+
}
133+
134+
if (len) {
135+
bool invert_flag = false;
136+
137+
if (len >= 3 && !nasm_memicmp(p, "no", 2)) {
138+
invert_flag = true;
139+
p += 2;
140+
len -= 2;
141+
}
112142

113-
iflag_set_cpu(&r, cpu->level);
114-
return r;
143+
for (cpuflag = cpunames; cpuflag->name; cpuflag++)
144+
if (!nasm_strnicmp(p, cpuflag->name, len))
145+
break;
146+
147+
if (!cpuflag->name) {
148+
nasm_nonfatal("unknown CPU type or flag '%.*s'", len, p);
149+
return;
150+
}
151+
152+
if (cpuflag->level >= IF_CPU_FIRST && cpuflag->level <= IF_ANY) {
153+
iflag_set_cpu(&cpu, cpuflag->level);
154+
} else {
155+
switch (modifier) {
156+
case '-':
157+
invert_flag = !invert_flag;
158+
break;
159+
case '*':
160+
invert_flag ^= iflag_test(&cmd_cpu, cpuflag->level);
161+
break;
162+
default:
163+
break;
164+
}
165+
166+
iflag_set(&cpu, cpuflag->level);
167+
if (invert_flag)
168+
iflag_clear(&cpu, cpuflag->level);
169+
}
170+
}
171+
p += len;
172+
if (!*p)
173+
break;
174+
p++; /* Skip separator */
175+
}
115176
}
116177

117178
static int get_bits(const char *value)
@@ -358,11 +419,11 @@ bool process_directives(char *directive)
358419

359420
if (!declare_label(value, type, special))
360421
break;
361-
422+
362423
if (type == LBL_COMMON || type == LBL_EXTERN || type == LBL_REQUIRED)
363424
define_label(value, 0, size, false);
364425

365-
break;
426+
break;
366427
}
367428

368429
case D_ABSOLUTE: /* [ABSOLUTE address] */
@@ -440,7 +501,7 @@ bool process_directives(char *directive)
440501
break;
441502

442503
case D_CPU: /* [CPU] */
443-
cpu = get_cpu(value);
504+
set_cpu(value);
444505
break;
445506

446507
case D_LIST: /* [LIST {+|-}] */

‎asm/nasm.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -131,8 +131,7 @@ struct optimization optimizing =
131131
{ MAX_OPTIMIZE, OPTIM_ALL_ENABLED }; /* number of optimization passes to take */
132132
static int cmd_sb = 16; /* by default */
133133

134-
iflag_t cpu;
135-
static iflag_t cmd_cpu;
134+
iflag_t cpu, cmd_cpu;
136135

137136
struct location location;
138137
bool in_absolute; /* Flag we are in ABSOLUTE seg */
@@ -525,8 +524,8 @@ int main(int argc, char **argv)
525524

526525
timestamp();
527526

528-
iflag_set_default_cpu(&cpu);
529-
iflag_set_default_cpu(&cmd_cpu);
527+
set_cpu(NULL);
528+
cmd_cpu = cpu;
530529

531530
set_default_limits();
532531

‎include/iflag.h

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@ IF_GEN_HELPER(xor, ^)
8585
/*
8686
* IF_ANY is the highest CPU level by definition
8787
*/
88-
#define IF_PLEVEL IF_ANY /* Default CPU level */
8988
#define IF_CPU_LEVEL_MASK ((IFM_ANY << 1) - 1)
9089

9190
static inline int iflag_cmp_cpu(const iflag_t *a, const iflag_t *b)
@@ -116,19 +115,6 @@ static inline void iflag_set_all_features(iflag_t *a)
116115
memset(p, -1, IF_FEATURE_NFIELDS * sizeof(uint32_t));
117116
}
118117

119-
static inline void iflag_set_cpu(iflag_t *a, unsigned int cpu)
120-
{
121-
a->field[0] = 0; /* Not applicable to the CPU type */
122-
iflag_set_all_features(a); /* All feature masking bits set for now */
123-
a->field[IF_CPU_FIELD] &= ~IF_CPU_LEVEL_MASK;
124-
iflag_set(a, cpu);
125-
}
126-
127-
static inline void iflag_set_default_cpu(iflag_t *a)
128-
{
129-
iflag_set_cpu(a, IF_PLEVEL);
130-
}
131-
132118
static inline iflag_t _iflag_pfmask(const iflag_t *a)
133119
{
134120
iflag_t r;

‎x86/iflags.ph

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ if_("AR2", "SB, SW, SD applies to argument 2");
2323
if_("AR3", "SB, SW, SD applies to argument 3");
2424
if_("AR4", "SB, SW, SD applies to argument 4");
2525
if_("OPT", "Optimizing assembly only");
26+
if_("LATEVEX", "Only if EVEX instructions are disabled");
2627

2728
#
2829
# dword bound - instruction feature filtering flags
@@ -141,8 +142,11 @@ if_("SANDYBRIDGE", "Sandy Bridge");
141142
if_("FUTURE", "Ivy Bridge or newer");
142143
if_("IA64", "IA64 (in x86 mode)");
143144

145+
# Default CPU level
146+
if_("DEFAULT", "Default CPU level");
147+
144148
# Must be the last CPU definition
145-
if_("ANY", "Any x86 CPU");
149+
if_("ANY", "Allow any known instruction");
146150

147151
# These must come after the CPU definitions proper
148152
if_("CYRIX", "Cyrix-specific");

‎x86/insns-iflags.ph

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -189,22 +189,32 @@ sub write_iflaggen_h() {
189189
}
190190
print N "\n";
191191

192-
# The names of fields
192+
# The names of flag groups
193193

194194
for ($i = 0; $i <= $#flag_fields; $i++) {
195-
printf N "#define %-19s %3d /* %-64s */\n",
196-
'IF_'.$flag_fields[$i]->[0].'_FIELD',
197-
$flag_fields[$i]->[1] >> 5,
198-
sprintf("IF_%s (%d) ... IF_%s (%d)",
195+
printf N "/* IF_%s (%d) ... IF_%s (%d) */\n",
199196
$flag_bynum[$flag_fields[$i]->[1]]->[1],
200197
$flag_bynum[$flag_fields[$i]->[1]]->[0],
201198
$flag_bynum[$flag_fields[$i]->[2]]->[1],
202-
$flag_bynum[$flag_fields[$i]->[2]]->[0]);
199+
$flag_bynum[$flag_fields[$i]->[2]]->[0];
200+
201+
# Bit definitions
202+
printf N "#define %-19s %3d\n",
203+
'IF_'.$flag_fields[$i]->[0].'_FIRST',
204+
$flag_fields[$i]->[1];
205+
printf N "#define %-19s %3d\n",
206+
'IF_'.$flag_fields[$i]->[0].'_COUNT',
207+
($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 1);
208+
209+
# Field (uint32) definitions
210+
printf N "#define %-19s %3d\n",
211+
'IF_'.$flag_fields[$i]->[0].'_FIELD',
212+
$flag_fields[$i]->[1] >> 5;
203213
printf N "#define %-19s %3d\n",
204214
'IF_'.$flag_fields[$i]->[0].'_NFIELDS',
205215
($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 31) >> 5;
216+
print N "\n";
206217
}
207-
print N "\n";
208218

209219
printf N "#define IF_FIELD_COUNT %d\n", $iflag_words;
210220
print N "typedef struct {\n";

‎x86/insns.dat

Lines changed: 39 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -3592,6 +3592,45 @@ SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTUR
35923592
SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE
35933593
SHA256RNDS2 xmmreg,xmmrm128 [rm: 0f 38 cb /r ] SHA,FUTURE
35943594

3595+
;# AVX no exception conversions
3596+
; Must precede AVX-512 versions
3597+
VBCSTNEBF16PS xmmreg,mem16 [rm: vex.128.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
3598+
VBCSTNEBF16PS ymmreg,mem16 [rm: vex.256.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
3599+
VBCSTNESH2PS xmmreg,mem16 [rm: vex.128.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
3600+
VBCSTNESH2PS ymmreg,mem16 [rm: vex.256.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
3601+
VCVTNEEBF162PS xmmreg,mem128 [rm: vex.128.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
3602+
VCVTNEEBF162PS ymmreg,mem256 [rm: vex.256.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
3603+
VCVTNEEPH2PS xmmreg,mem128 [rm: vex.128.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
3604+
VCVTNEEPH2PS ymmreg,mem256 [rm: vex.256.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
3605+
VCVTNEOBF162PS xmmreg,mem128 [rm: vex.128.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
3606+
VCVTNEOBF162PS ymmreg,mem256 [rm: vex.256.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
3607+
VCVTNEOPH2PS xmmreg,mem128 [rm: vex.128.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
3608+
VCVTNEOPH2PS ymmreg,mem256 [rm: vex.256.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
3609+
VCVTNEPS2BF16 xmmreg,xmmrm128 [rm: vex.128.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
3610+
VCVTNEPS2BF16 ymmreg,ymmrm256 [rm: vex.256.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
3611+
3612+
;# AVX Vector Neural Network Instructions
3613+
; Must precede AVX-512 versions
3614+
VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3615+
VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3616+
VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3617+
VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3618+
VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3619+
VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3620+
VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3621+
VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3622+
VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3623+
VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3624+
VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
3625+
VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
3626+
3627+
;# AVX Integer Fused Multiply-Add
3628+
; Must precede AVX-512 versions
3629+
VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SX
3630+
VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SY
3631+
VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SX
3632+
VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SY
3633+
35953634
;# AVX-512 mask register instructions
35963635
KADDB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4a /r ] FUTURE
35973636
KADDD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 4a /r ] FUTURE
@@ -6307,42 +6346,6 @@ VSUBPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.np.map5.w0 5
63076346
VSUBSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 5c /r] AVX512FP16,FUTURE
63086347
VUCOMISH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.np.map5.w0 2e /r] AVX512FP16,FUTURE
63096348

6310-
;# AVX no exception conversions
6311-
VBCSTNEBF16PS xmmreg,mem16 [rm: vex.128.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
6312-
VBCSTNEBF16PS ymmreg,mem16 [rm: vex.256.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
6313-
VBCSTNESH2PS xmmreg,mem16 [rm: vex.128.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
6314-
VBCSTNESH2PS ymmreg,mem16 [rm: vex.256.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,SW
6315-
VCVTNEEBF162PS xmmreg,mem128 [rm: vex.128.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
6316-
VCVTNEEBF162PS ymmreg,mem256 [rm: vex.256.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
6317-
VCVTNEEPH2PS xmmreg,mem128 [rm: vex.128.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
6318-
VCVTNEEPH2PS ymmreg,mem256 [rm: vex.256.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
6319-
VCVTNEOBF162PS xmmreg,mem128 [rm: vex.128.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
6320-
VCVTNEOBF162PS ymmreg,mem256 [rm: vex.256.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
6321-
VCVTNEOPH2PS xmmreg,mem128 [rm: vex.128.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SX
6322-
VCVTNEOPH2PS ymmreg,mem256 [rm: vex.256.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,SY
6323-
VCVTNEPS2BF16 xmmreg,xmmrm128 [rm: vex.128.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,SX
6324-
VCVTNEPS2BF16 ymmreg,ymmrm256 [rm: vex.256.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,SY
6325-
6326-
;# AVX Vector Neural Network Instructions
6327-
VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
6328-
VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
6329-
VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
6330-
VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
6331-
VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
6332-
VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
6333-
VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
6334-
VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
6335-
VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SX
6336-
VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,SY
6337-
VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SX
6338-
VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,SY
6339-
6340-
;# AVX Integer Fused Multiply-Add
6341-
VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,SX
6342-
VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,SY
6343-
VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,SX
6344-
VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,SY
6345-
63466349
;# RAO-INT weakly ordered atomic operations
63476350
AADD mem32,reg32 [mr: norexw np 0f 38 fc /r ] RAOINT,FUTURE,SD
63486351
AADD mem64,reg64 [mr: o64 np 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG

0 commit comments

Comments
 (0)