PLL numbers swapped for Bergen Board

[KyleM32767]

On the CW310 Bergen Board, the numbers of the PLL outputs when calling target.pll methods do not correspond to the correct PLL output numbers. (i.e. calling target.pll.pll_outenable_set(True, 2) enables PLL output 1, and vice versa).

Looking at the schematic and constraint file, it seems like this is because the signals for PLL_CLK1 and PLL_CLK2 are on pins Y4 and Y1, respectively of the external PLL.

#####
# Input Clocks
#####

set_property -dict { PACKAGE_PIN  R22  IOSTANDARD   LVCMOS33 } [get_ports { PLL_CLK1 }]; #IO_L14P_T2_SRCC_13
set_property -dict { PACKAGE_PIN  N21  IOSTANDARD   LVCMOS33 } [get_ports { PLL_CLK2 }]; #IO_L12P_T1_MRCC_13

However the API assumes PLL_CLK1 is on pin Y1 and PLL_CLK2 is on Y4...

    def outputUpdateOutputs(self, outnum, pllsrc_new=None, pllenabled_new=None, pllslewrate_new=None):
        """Update the output pins with enabled/disabled, slew rate, etc"""
        outnum = self.swap_340_pllnum(outnum)
        # Map to output pins on CDCE906 Chip
        if outnum == 0:
            outpin = 0
            if pllsrc_new is None:
                src = self._pll0source
            else:
                src = pllsrc_new

            if src == 'PLL0':
                divsrc = 0
            elif src == 'PLL1':
                divsrc = 1
            elif src == 'PLL2':
                divsrc = 2
        elif outnum == 1:
            outpin = 1
            divsrc = 1
        elif outnum == 2:
            outpin = 4
            divsrc = 2

The CW305 is that way, which tells me this is just a mistake with the CW310 design.

TLDR: Switch the labels for PLL_CLK1 and PLL_CLK2 on the schematic and bergen.xdc