updated max reg offset

Author: Salvador Santoluctio

labview_fpga_hdl_tools/common.py

@@ -243,8 +243,8 @@ def load_config(config_path=None):
     files.lv_target_menus_folder = resolve_path(settings.get("LVTargetMenusFolder"))
     files.lv_target_info_ini = resolve_path(settings.get("LVTargetInfoIni"))
     files.lv_target_exclude_files = resolve_path(settings.get("LVTargetExcludeFiles"))
-    num_hdl_registers_str = settings.get("NumHdlRegisters")
-    files.num_hdl_registers = int(num_hdl_registers_str) if num_hdl_registers_str else None
+    max_hdl_reg_offset_str = settings.get("MaxHdlRegOffset")
+    files.max_hdl_reg_offset = int(max_hdl_reg_offset_str) if max_hdl_reg_offset_str else None
 
     # -----------------------------------------------------------------------
     # Load CLIP migration settings

labview_fpga_hdl_tools/gen_labview_target_plugin.py

@@ -439,7 +439,7 @@ def _generate_target_xml(
     clock_path,
     lv_target_name,
     lv_target_guid,
-    num_hdl_registers,
+    max_hdl_reg_offset,
 ):
     """Generate Target XML files from multiple Mako templates.
 
@@ -455,7 +455,7 @@ def _generate_target_xml(
         clock_path (str): Path to the Clock XML (for filename extraction)
         lv_target_name (str): Name of the LabVIEW FPGA target
         lv_target_guid (str): GUID for the LabVIEW FPGA target
-        num_hdl_registers (int): Number of HDL registers
+        max_hdl_reg_offset (int): Maximum HDL register offset (byte address)
 
     Raises:
         SystemExit: If an error occurs during XML generation
@@ -465,9 +465,9 @@ def _generate_target_xml(
         boardio_filename = os.path.basename(boardio_path)
         clock_filename = os.path.basename(clock_path)
 
-        # Calculate min_lv_reg_offset from num_hdl_registers
-        # Formula: num_hdl_registers * 4, converted to hex with 5 hex digits (0x00000 format)
-        offset_value = num_hdl_registers * 4 if num_hdl_registers is not None else 0
+        # Calculate min_lv_reg_offset from max_hdl_reg_offset
+        # Formula: max_hdl_reg_offset + 4 (next 32-bit register), converted to hex with 5 hex digits (0x00000 format)
+        offset_value = max_hdl_reg_offset + 4 if max_hdl_reg_offset is not None else 0
         min_lv_reg_offset = f"0x{offset_value:05X}"
 
         # Ensure output directory exists
@@ -812,7 +812,7 @@ def gen_lv_target_support():
         config.clock_output,
         config.lv_target_name,
         config.lv_target_guid,
-        config.num_hdl_registers,
+        config.max_hdl_reg_offset,
     )
 
     _copy_fpgafiles(