Skip to content

Commit 66b80d7

Browse files
author
Salvador Santoluctio
committed
working on tests
1 parent 7303192 commit 66b80d7

20 files changed

+1107
-1618
lines changed

‎tests/test-labview-vpe/VivadoProject/TheWindowFlatWrapper.v‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
// Mock Verilog netlist file created for testing

‎tests/test-project/deps/flexrio-deps/flexrio-deps/DFlop.vhd‎

Lines changed: 3 additions & 147 deletions
Original file line numberDiff line numberDiff line change
@@ -1,147 +1,3 @@
1-
-------------------------------------------------------------------------------
2-
--
3-
-- File: DFlop.vhd
4-
-- Author: Tamas Gyorfi
5-
-- Original Project: Vivado support for 7-series LabVIEW FPGA targets
6-
-- Date: 16 July 2013
7-
--
8-
-------------------------------------------------------------------------------
9-
-- (c) 2013 Copyright National Instruments Corporation
10-
-- All Rights Reserved
11-
-- National Instruments Internal Information
12-
-------------------------------------------------------------------------------
13-
--
14-
-- Purpose:
15-
-- This creates a flip-flop using either the FDCE or FDPE Xilinx
16-
-- primitives, depending on the desired async. reset value of the Flop.
17-
-- The implementation described in this component is specific to Vivado,
18-
-- since Vivado no longer supports the FDCPE primitive on newer FPGAs (>V6).
19-
--
20-
-- The kAsyncReg generic is helping to set the ASYNC_REG attribute
21-
-- for the instantiated FDCE or FDPE primitives.
22-
-- This cannot be done from the upper levels where the DFlop is instantiated,
23-
-- since the attribute can not propagate from the net to his driver FF.
24-
-- We set the default value to "false" so the already existing instances
25-
-- would not require to be updated.
26-
27-
-- The ASYNC_REG attribute affects optimization, placement, and routing to improve Mean
28-
-- Time Between Failure (MTBF) for registers that may go metastable. If ASYNC_REG is applied,
29-
-- the placer will ensure the flip-flops on a synchronization chain are placed closely to
30-
-- maximize MTBF. Registers with ASYNC_REG that are directly connected will be grouped and
31-
-- placed together into a single SLICE, assuming they have a compatible control set and the
32-
-- number of registers does not exceed the available resources of the SLICE
33-
--
34-
-- Asrar Rangwala July 12 2023: Minor changes were manually made to this file to make it compile with
35-
-- vsmake. A better long term fix would be to upgrade LV FPGA's version of NICores to the latest.
36-
-- However, that's a non-trivial task and unlikely to be prioritized unless necessary.
37-
-- Since, there is a quick workaround available, we have opted to apply a manual
38-
-- change to this file rather than update it to an official export of the NICores.
39-
-------------------------------------------------------------------------------
40-
41-
library ieee;
42-
use ieee.std_logic_1164.all;
43-
44-
library work;
45-
use work.PkgNiUtilities.all;
46-
47-
library UNISIM;
48-
use UNISIM.vcomponents.all;
49-
50-
entity DFlop is
51-
52-
generic (kResetVal : std_logic := '0';
53-
kAsyncReg : string := "false");
54-
port (
55-
aReset, cEn : in boolean;
56-
Clk, cD : in std_logic;
57-
cQ : out std_logic := kResetVal
58-
);
59-
end DFlop;
60-
61-
architecture rtl of DFlop is
62-
attribute ASYNC_REG : string;
63-
begin
64-
65-
-- This VScan model helps VScan analyze this as a flip-flop and not
66-
-- be fooled by the delta delay that occurs on the PRE and CLR signals.
67-
GenVScanModel: if false generate
68-
process (aReset, Clk)
69-
begin
70-
if aReset then
71-
cQ <= '0';
72-
elsif rising_edge(Clk) then
73-
if cEn then cQ <= cD; end if;
74-
end if;
75-
end process;
76-
end generate GenVScanModel;
77-
78-
--vscan vscan_off
79-
80-
-- !!NOTE:
81-
-- If you change the instance names in this component, consider updating
82-
-- DFlop module generator as well: vi.lib\rvi\nicores\ClockBoundaryCrossing\DFlopBaseniFpgaDflopInstanceName.vi
83-
84-
GenClr: if kResetVal='0' generate
85-
attribute ASYNC_REG of ClearFDCPEx : label is kAsyncReg;
86-
begin
87-
-- Generate Flop with asynchronous clear
88-
89-
--vhook_i FDCE ClearFDCPEx
90-
--vhook_a INIT '0'
91-
--vhook_a IS_CLR_INVERTED '0'
92-
--vhook_a IS_C_INVERTED '0'
93-
--vhook_a IS_D_INVERTED '0'
94-
--vhook_a CLR To_StdLogic(aReset)
95-
--vhook_a C Clk
96-
--vhook_a CE To_StdLogic(cEn)
97-
--vhook_a D cD
98-
--vhook_a Q cQ
99-
ClearFDCPEx: FDCE
100-
generic map (
101-
INIT => '0', --bit:='0'
102-
IS_CLR_INVERTED => '0', --bit:='0'
103-
IS_C_INVERTED => '0', --bit:='0'
104-
IS_D_INVERTED => '0') --bit:='0'
105-
port map (
106-
Q => cQ, --out std_ulogic:=TO_X01(INIT)
107-
C => Clk, --in std_ulogic
108-
CE => To_StdLogic(cEn), --in std_ulogic
109-
CLR => To_StdLogic(aReset), --in std_ulogic
110-
D => cD); --in std_ulogic
111-
112-
end generate GenClr;
113-
114-
GenSet: if kResetVal='1' generate
115-
attribute ASYNC_REG of PresetFDCPEx : label is kAsyncReg;
116-
begin
117-
-- Generate Flop with asynchronous preset
118-
119-
--vhook_i FDPE PresetFDCPEx
120-
--vhook_a INIT '1'
121-
--vhook_a IS_CLR_INVERTED '0'
122-
--vhook_a IS_C_INVERTED '0'
123-
--vhook_a IS_D_INVERTED '0'
124-
--vhook_a IS_PRE_INVERTED '0'
125-
--vhook_a PRE To_StdLogic(aReset)
126-
--vhook_a C Clk
127-
--vhook_a CE To_StdLogic(cEn)
128-
--vhook_a D cD
129-
--vhook_a Q cQ
130-
PresetFDCPEx: FDPE
131-
generic map (
132-
INIT => '1', --bit:='1'
133-
IS_C_INVERTED => '0', --bit:='0'
134-
IS_D_INVERTED => '0', --bit:='0'
135-
IS_PRE_INVERTED => '0') --bit:='0'
136-
port map (
137-
Q => cQ, --out std_ulogic:=TO_X01(INIT)
138-
C => Clk, --in std_ulogic
139-
CE => To_StdLogic(cEn), --in std_ulogic
140-
D => cD, --in std_ulogic
141-
PRE => To_StdLogic(aReset)); --in std_ulogic
142-
143-
end generate GenSet;
144-
145-
--vscan vscan_on
146-
147-
end rtl;
1+
----------------------------------------------
2+
-- IMPLEMENTATION NOT NEEDED FOR TESTING
3+
----------------------------------------------

‎tests/test-project/deps/flexrio-deps/flexrio-deps/DFlopBoolVec.vhd‎

Lines changed: 3 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,3 @@
1-
-------------------------------------------------------------------------------
2-
--
3-
-- File: DFlopBoolVec.vhd
4-
-- Author: Craig Conway
5-
-- Original Project: SMC4
6-
-- Date: 28 November 2006
7-
--
8-
-------------------------------------------------------------------------------
9-
-- (c) 2006 Copyright National Instruments Corporation
10-
-- All Rights Reserved
11-
-- National Instruments Internal Information
12-
-------------------------------------------------------------------------------
13-
--
14-
-- Purpose:
15-
-- Instantiates an array of DFlop components. These components
16-
-- have a "hard" syn_hier attribute so that the enable logic won't
17-
-- get merged with the D logic.
18-
--
19-
-------------------------------------------------------------------------------
20-
21-
library ieee;
22-
use ieee.std_logic_1164.all;
23-
24-
library work;
25-
use work.PkgNiUtilities.all;
26-
27-
entity DFlopBoolVec is
28-
generic (kResetVal : BooleanVector);
29-
port (
30-
aReset, cEn : in boolean;
31-
Clk : in std_logic;
32-
cD : in BooleanVector(kResetVal'length-1 downto 0);
33-
cQ : out BooleanVector(kResetVal'length-1 downto 0) := kResetVal
34-
);
35-
end DFlopBoolVec;
36-
37-
architecture rtl of DFlopBoolVec is
38-
39-
signal cQ_SLV: std_logic_vector(kResetVal'length-1 downto 0);
40-
41-
begin
42-
43-
--vhook_e DFlopSLV
44-
--vhook_a kResetVal To_StdLogicVector(kResetVal)
45-
--vhook_a cD To_StdLogicVector(cD)
46-
--vhook_a cQ cQ_SLV
47-
DFlopSLVx: entity work.DFlopSLV (rtl)
48-
generic map (
49-
kResetVal => To_StdLogicVector(kResetVal)) -- in std_logic_vector
50-
port map (
51-
aReset => aReset, -- in boolean
52-
cEn => cEn, -- in boolean
53-
Clk => Clk, -- in std_logic
54-
cD => To_StdLogicVector(cD), -- in std_logic_vector(kResetVal'length-1 downto
55-
cQ => cQ_SLV); -- out std_logic_vector(kResetVal'length-1 downto
56-
57-
cQ <= to_BooleanVector(cQ_SLV);
58-
59-
end rtl;
60-
61-
-- The following comment is a checksum VScan uses to determine whether this
62-
-- file has been modified. Please don't try to get around it. It's there
63-
-- for a reason.
64-
--VScan_CS 5679021
1+
----------------------------------------------
2+
-- IMPLEMENTATION NOT NEEDED FOR TESTING
3+
----------------------------------------------

‎tests/test-project/deps/flexrio-deps/flexrio-deps/DFlopSLV.vhd‎

Lines changed: 3 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -1,67 +1,3 @@
1-
-------------------------------------------------------------------------------
2-
--
3-
-- File: DFlopSLV.vhd
4-
-- Author: Craig Conway
5-
-- Original Project: SMC4
6-
-- Date: 28 November 2006
7-
--
8-
-------------------------------------------------------------------------------
9-
-- (c) 2006 Copyright National Instruments Corporation
10-
-- All Rights Reserved
11-
-- National Instruments Internal Information
12-
-------------------------------------------------------------------------------
13-
--
14-
-- Purpose:
15-
-- Instantiates an array flip-flops with a "hard" syn_hier attribute so
16-
-- that the enable logic won't get merged with the D logic.
17-
-- This file does not synthesize under XST in ISE 10.1 or earlier
18-
-- because of a bug where XST does not support using the 'length attribute
19-
-- of a generic. You can use DFlopSlvResetVal for XST instead.
20-
--
21-
-------------------------------------------------------------------------------
22-
23-
library ieee;
24-
use ieee.std_logic_1164.all;
25-
26-
entity DFlopSLV is
27-
generic (kResetVal : std_logic_vector;
28-
kAsyncReg : string := "false");
29-
port (
30-
aReset, cEn : in boolean;
31-
Clk : in std_logic;
32-
cD : in std_logic_vector(kResetVal'length-1 downto 0);
33-
cQ : out std_logic_vector(kResetVal'length-1 downto 0) := kResetVal
34-
);
35-
end DFlopSLV;
36-
37-
architecture rtl of DFlopSLV is
38-
39-
constant kRstVec : std_logic_vector(kResetVal'length-1 downto 0) := kResetVal;
40-
41-
begin
42-
43-
GenFlops: for i in 0 to kResetVal'length-1 generate
44-
45-
--vhook_e DFlop
46-
--vhook_a kResetVal kRstVec(i)
47-
--vhook_a cD cD(i)
48-
--vhook_a cQ cQ(i)
49-
DFlopx: entity work.DFlop (rtl)
50-
generic map (
51-
kResetVal => kRstVec(i),
52-
kAsyncReg => kAsyncReg)
53-
port map (
54-
aReset => aReset,
55-
cEn => cEn,
56-
Clk => Clk,
57-
cD => cD(i),
58-
cQ => cQ(i));
59-
60-
end generate;
61-
62-
end rtl;
63-
64-
-- The following comment is a checksum VScan uses to determine whether this
65-
-- file has been modified. Please don't try to get around it. It's there
66-
-- for a reason.
67-
--VScan_CS 5302020
1+
----------------------------------------------
2+
-- IMPLEMENTATION NOT NEEDED FOR TESTING
3+
----------------------------------------------

‎tests/test-project/deps/flexrio-deps/flexrio-deps/DFlopUnsigned.vhd‎

Lines changed: 3 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,3 @@
1-
-------------------------------------------------------------------------------
2-
--
3-
-- File: DFlopUnsigned.vhd
4-
-- Author: Craig Conway
5-
-- Original Project: SMC4
6-
-- Date: 28 November 2006
7-
--
8-
-------------------------------------------------------------------------------
9-
-- (c) 2006 Copyright National Instruments Corporation
10-
-- All Rights Reserved
11-
-- National Instruments Internal Information
12-
-------------------------------------------------------------------------------
13-
--
14-
-- Purpose:
15-
-- Instantiates an array of DFlop components. These components
16-
-- have a "hard" syn_hier attribute so that the enable logic won't
17-
-- get merged with the D logic.
18-
--
19-
-------------------------------------------------------------------------------
20-
21-
library ieee;
22-
use ieee.std_logic_1164.all;
23-
use ieee.numeric_std.all;
24-
25-
entity DFlopUnsigned is
26-
generic (kResetVal : unsigned);
27-
port (
28-
aReset, cEn : in boolean;
29-
Clk : in std_logic;
30-
cD : in unsigned(kResetVal'length-1 downto 0);
31-
cQ : out unsigned(kResetVal'length-1 downto 0) := kResetVal
32-
);
33-
end DFlopUnsigned;
34-
35-
architecture rtl of DFlopUnsigned is
36-
37-
begin
38-
39-
GenFlops: for i in 0 to kResetVal'length-1 generate
40-
41-
--vhook_e DFlop
42-
--vhook_a kResetVal kResetVal(i)
43-
--vhook_a kAsyncReg "false"
44-
--vhook_a cD cD(i)
45-
--vhook_a cQ cQ(i)
46-
DFlopx: entity work.DFlop (rtl)
47-
generic map (
48-
kResetVal => kResetVal(i), --std_logic:='0'
49-
kAsyncReg => "false") --string:="false"
50-
port map (
51-
aReset => aReset, --in boolean
52-
cEn => cEn, --in boolean
53-
Clk => Clk, --in std_logic
54-
cD => cD(i), --in std_logic
55-
cQ => cQ(i)); --out std_logic:=kResetVal
56-
57-
end generate;
58-
59-
end rtl;
60-
61-
-- The following comment is a checksum VScan uses to determine whether this
62-
-- file has been modified. Please don't try to get around it. It's there
63-
-- for a reason.
64-
--VScan_CS 4791120
1+
----------------------------------------------
2+
-- IMPLEMENTATION NOT NEEDED FOR TESTING
3+
----------------------------------------------

0 commit comments

Comments
 (0)