hw: replace apb_uart with obi_uart (pulp-platform#61)

* hw: replace apb_uart with obi_uart

apb_uart implements only 16750 (larger FIFO)

obi_uart was developed by students at ETHZ.
It implements 16550A (smaller), with plans
to add an optional 16750 mode in the future.
This and native obi makes obi_uart a better fit
for smaller systems like croc.

* test: add uart receive check via loopback mode

* sw: fix relocation truncated to fit error

Author: phsauter

.github/scripts/check_sim.sh

@@ -12,6 +12,7 @@ expected_lines=(
   "\[JTAG\] Halting hart 0"
   "\[JTAG\] Resumed hart 0"
   "\[UART\] Hello World!"
+  "\[UART\] Loopback received: internal msg"
   "\[UART\] Result: 0x8940, Cycles: 0xBD"
   "\[UART\] Tick"
   "\[UART\] Tock"

Bender.local

@@ -4,7 +4,7 @@ overrides:
   common_cells: { path: "rtl/common_cells" }
   apb: { path: "rtl/apb" }
   register_interface: { path: "rtl/register_interface" }
-  apb_uart: { path: "rtl/apb_uart" }
+  obi_peripherals: { path: "rtl/obi_uart" }
   ibex: { path: "rtl/ibex" }
   obi: { path: "rtl/obi" }
   riscv-dbg: { path: "rtl/riscv-dbg" }

croc.flist

@@ -1,20 +1,3 @@
-# Copyright (c) 2025 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Authors:
-# - Philippe Sauter <[email protected]>
-
-# List of files to synthesize the design
-# A file list given to the yosys-slang frontend to load the design
-# In this flow we use 'read_slang -F croc.flist' to load this file
-# All paths are relative to this file (use -f to make them relative to CWD)
-# It contains:
-# - include directores expected from SystemVerilog 'include' statements
-# - defines used in some SystemVerilog files
-#   often used to guard non-synthesisable code or select some implementation
-# - the paths to all source files
-
 +incdir+rtl/apb/include
 +incdir+rtl/common_cells/include
 +incdir+rtl/cve2/include
@@ -108,27 +91,16 @@ rtl/common_cells/stream_arbiter.sv
 rtl/common_cells/stream_omega_net.sv
 rtl/common_cells/mem_to_banks.sv
 rtl/apb/apb_pkg.sv
-rtl/register_interface/reg_intf.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
-rtl/register_interface/periph_to_reg.sv
-rtl/register_interface/reg_to_apb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
-rtl/apb_uart/slib_clock_div.sv
-rtl/apb_uart/slib_counter.sv
-rtl/apb_uart/slib_edge_detect.sv
-rtl/apb_uart/slib_fifo.sv
-rtl/apb_uart/slib_input_filter.sv
-rtl/apb_uart/slib_input_sync.sv
-rtl/apb_uart/slib_mv_filter.sv
-rtl/apb_uart/uart_baudgen.sv
-rtl/apb_uart/uart_interrupt.sv
-rtl/apb_uart/uart_receiver.sv
-rtl/apb_uart/uart_transmitter.sv
-rtl/apb_uart/apb_uart.sv
-rtl/apb_uart/apb_uart_wrap.sv
-rtl/apb_uart/reg_uart_wrap.sv
+rtl/obi/obi_pkg.sv
+rtl/obi/obi_intf.sv
+rtl/obi/obi_rready_converter.sv
+rtl/obi/obi_atop_resolver.sv
+rtl/obi/obi_cut.sv
+rtl/obi/obi_demux.sv
+rtl/obi/obi_err_sbr.sv
+rtl/obi/obi_mux.sv
+rtl/obi/obi_sram_shim.sv
+rtl/obi/obi_xbar.sv
 rtl/cve2/cve2_pkg.sv
 rtl/cve2/cve2_alu.sv
 rtl/cve2/cve2_compressed_decoder.sv
@@ -149,15 +121,21 @@ rtl/cve2/cve2_id_stage.sv
 rtl/cve2/cve2_prefetch_buffer.sv
 rtl/cve2/cve2_if_stage.sv
 rtl/cve2/cve2_core.sv
-rtl/obi/obi_pkg.sv
-rtl/obi/obi_intf.sv
-rtl/obi/obi_rready_converter.sv
-rtl/obi/obi_atop_resolver.sv
-rtl/obi/obi_demux.sv
-rtl/obi/obi_err_sbr.sv
-rtl/obi/obi_mux.sv
-rtl/obi/obi_sram_shim.sv
-rtl/obi/obi_xbar.sv
+rtl/obi_uart/obi_uart_pkg.sv
+rtl/obi_uart/obi_uart_baudgen.sv
+rtl/obi_uart/obi_uart_interrupts.sv
+rtl/obi_uart/obi_uart_modem.sv
+rtl/obi_uart/obi_uart_rx.sv
+rtl/obi_uart/obi_uart_tx.sv
+rtl/obi_uart/obi_uart_register.sv
+rtl/obi_uart/obi_uart.sv
+rtl/register_interface/reg_intf.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
+rtl/register_interface/periph_to_reg.sv
+rtl/register_interface/reg_to_apb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
 rtl/riscv-dbg/dm_pkg.sv
 rtl/riscv-dbg/debug_rom/debug_rom.sv
 rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv