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[RISCV][FPEnv] Lowering of fpmode intrinsics (llvm#148569)
The change implements custom lowering of `get_fpmode`, `set_fpmode` and `reset_fpmode` for RISCV target. The implementation is aligned with the functions `fegetmode` and `fesetmode` in GLIBC.
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,17 @@ inline static bool isValidRoundingMode(unsigned Mode) {
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}
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} // namespace RISCVVXRndMode
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497+
namespace RISCVExceptFlags {
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enum ExceptionFlag {
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NX = 0x01, // Inexact
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UF = 0x02, // Underflow
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OF = 0x04, // Overflow
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DZ = 0x08, // Divide by zero
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NV = 0x10, // Invalid operation
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ALL = 0x1F // Mask for all accrued exception flags
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};
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}
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497508
//===----------------------------------------------------------------------===//
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// Floating-point Immediates
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//

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -655,6 +655,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::GET_FPENV, XLenVT, Custom);
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setOperationAction(ISD::SET_FPENV, XLenVT, Custom);
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setOperationAction(ISD::RESET_FPENV, MVT::Other, Custom);
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setOperationAction(ISD::GET_FPMODE, XLenVT, Custom);
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setOperationAction(ISD::SET_FPMODE, XLenVT, Custom);
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setOperationAction(ISD::RESET_FPMODE, MVT::Other, Custom);
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}
659662

660663
setOperationAction({ISD::GlobalAddress, ISD::BlockAddress, ISD::ConstantPool,
@@ -8225,6 +8228,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerSET_FPENV(Op, DAG);
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case ISD::RESET_FPENV:
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return lowerRESET_FPENV(Op, DAG);
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case ISD::GET_FPMODE:
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return lowerGET_FPMODE(Op, DAG);
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case ISD::SET_FPMODE:
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return lowerSET_FPMODE(Op, DAG);
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case ISD::RESET_FPMODE:
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return lowerRESET_FPMODE(Op, DAG);
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case ISD::EH_DWARF_CFA:
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return lowerEH_DWARF_CFA(Op, DAG);
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case ISD::VP_MERGE:
@@ -14002,6 +14011,54 @@ SDValue RISCVTargetLowering::lowerRESET_FPENV(SDValue Op,
1400214011
EnvValue);
1400314012
}
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14014+
const uint64_t ModeMask64 = ~RISCVExceptFlags::ALL;
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const uint32_t ModeMask32 = ~RISCVExceptFlags::ALL;
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14017+
SDValue RISCVTargetLowering::lowerGET_FPMODE(SDValue Op,
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SelectionDAG &DAG) const {
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const MVT XLenVT = Subtarget.getXLenVT();
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const uint64_t ModeMaskValue = Subtarget.is64Bit() ? ModeMask64 : ModeMask32;
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SDLoc DL(Op);
14022+
SDValue Chain = Op->getOperand(0);
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SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
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SDValue ModeMask = DAG.getConstant(ModeMaskValue, DL, XLenVT);
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SDVTList VTs = DAG.getVTList(XLenVT, MVT::Other);
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SDValue Result = DAG.getNode(RISCVISD::READ_CSR, DL, VTs, Chain, SysRegNo);
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Chain = Result.getValue(1);
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return DAG.getMergeValues({Result, Chain}, DL);
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}
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SDValue RISCVTargetLowering::lowerSET_FPMODE(SDValue Op,
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SelectionDAG &DAG) const {
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const MVT XLenVT = Subtarget.getXLenVT();
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const uint64_t ModeMaskValue = Subtarget.is64Bit() ? ModeMask64 : ModeMask32;
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SDLoc DL(Op);
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SDValue Chain = Op->getOperand(0);
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SDValue EnvValue = Op->getOperand(1);
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SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
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SDValue ModeMask = DAG.getConstant(ModeMaskValue, DL, XLenVT);
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EnvValue = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, EnvValue);
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EnvValue = DAG.getNode(ISD::AND, DL, XLenVT, EnvValue, ModeMask);
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Chain = DAG.getNode(RISCVISD::CLEAR_CSR, DL, MVT::Other, Chain, SysRegNo,
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ModeMask);
14045+
return DAG.getNode(RISCVISD::SET_CSR, DL, MVT::Other, Chain, SysRegNo,
14046+
EnvValue);
14047+
}
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14049+
SDValue RISCVTargetLowering::lowerRESET_FPMODE(SDValue Op,
14050+
SelectionDAG &DAG) const {
14051+
const MVT XLenVT = Subtarget.getXLenVT();
14052+
const uint64_t ModeMaskValue = Subtarget.is64Bit() ? ModeMask64 : ModeMask32;
14053+
SDLoc DL(Op);
14054+
SDValue Chain = Op->getOperand(0);
14055+
SDValue SysRegNo = DAG.getTargetConstant(RISCVSysReg::fcsr, DL, XLenVT);
14056+
SDValue ModeMask = DAG.getConstant(ModeMaskValue, DL, XLenVT);
14057+
14058+
return DAG.getNode(RISCVISD::CLEAR_CSR, DL, MVT::Other, Chain, SysRegNo,
14059+
ModeMask);
14060+
}
14061+
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SDValue RISCVTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
1400614063
SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -563,6 +563,9 @@ class RISCVTargetLowering : public TargetLowering {
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SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
564564
SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
565565
SDValue lowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
567+
SDValue lowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
568+
SDValue lowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
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567570
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
568571
SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,20 @@ def riscv_swap_csr : RVSDNode<"SWAP_CSR",
120120
SDTCisInt<2>]>,
121121
[SDNPHasChain]>;
122122

123+
// Clear bits of CSR. The first operand is the address of the required CSR,
124+
// the second is the bitmask of cleared bits.
125+
def riscv_clear_csr : RVSDNode<"CLEAR_CSR",
126+
SDTypeProfile<0, 2, [SDTCisInt<0>,
127+
SDTCisInt<1>]>,
128+
[SDNPHasChain]>;
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130+
// Set bits of CSR. The first operand is the address of the required CSR,
131+
// the second is the bitmask of bits to set.
132+
def riscv_set_csr : RVSDNode<"SET_CSR",
133+
SDTypeProfile<0, 2, [SDTCisInt<0>,
134+
SDTCisInt<1>]>,
135+
[SDNPHasChain]>;
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123137
// A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
124138
// It takes a chain operand and another two target constant operands (the
125139
// CSR numbers of the low and high parts of the counter).
@@ -2038,6 +2052,42 @@ class SwapSysRegImm<SysReg SR, list<Register> Regs>
20382052
let Defs = Regs;
20392053
}
20402054

2055+
class ClearSysReg<SysReg SR, list<Register> Regs>
2056+
: Pseudo<(outs), (ins GPR:$val),
2057+
[(riscv_clear_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>,
2058+
PseudoInstExpansion<(CSRRC X0, SR.Encoding, GPR:$val)> {
2059+
let hasSideEffects = 0;
2060+
let Uses = Regs;
2061+
let Defs = Regs;
2062+
}
2063+
2064+
class ClearSysRegImm<SysReg SR, list<Register> Regs>
2065+
: Pseudo<(outs), (ins uimm5:$val),
2066+
[(riscv_clear_csr (XLenVT SR.Encoding), uimm5:$val)]>,
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PseudoInstExpansion<(CSRRCI X0, SR.Encoding, uimm5:$val)> {
2068+
let hasSideEffects = 0;
2069+
let Uses = Regs;
2070+
let Defs = Regs;
2071+
}
2072+
2073+
class SetSysReg<SysReg SR, list<Register> Regs>
2074+
: Pseudo<(outs), (ins GPR:$val),
2075+
[(riscv_set_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>,
2076+
PseudoInstExpansion<(CSRRS X0, SR.Encoding, GPR:$val)> {
2077+
let hasSideEffects = 0;
2078+
let Uses = Regs;
2079+
let Defs = Regs;
2080+
}
2081+
2082+
class SetSysRegImm<SysReg SR, list<Register> Regs>
2083+
: Pseudo<(outs), (ins uimm5:$val),
2084+
[(riscv_set_csr (XLenVT SR.Encoding), uimm5:$val)]>,
2085+
PseudoInstExpansion<(CSRRSI X0, SR.Encoding, uimm5:$val)> {
2086+
let hasSideEffects = 0;
2087+
let Uses = Regs;
2088+
let Defs = Regs;
2089+
}
2090+
20412091
def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
20422092
let hasPostISelHook = 1 in {
20432093
def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
@@ -2056,6 +2106,10 @@ let hasPostISelHook = 1 in {
20562106
def ReadFCSR : ReadSysReg<SysRegFCSR, [FRM, FFLAGS]>;
20572107
def WriteFCSR : WriteSysReg<SysRegFCSR, [FRM, FFLAGS]>;
20582108
def WriteFCSRImm : WriteSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
2109+
def ClearFCSR : ClearSysReg<SysRegFCSR, [FRM, FFLAGS]>;
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def ClearFCSRImm : ClearSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
2111+
def SetFCSR : SetSysReg<SysRegFCSR, [FRM, FFLAGS]>;
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def SetFCSRImm : SetSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
20592113
}
20602114

20612115
/// Other pseudo-instructions

‎llvm/test/CodeGen/RISCV/fpenv-xlen.ll

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Original file line numberDiff line numberDiff line change
@@ -35,3 +35,37 @@ entry:
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call void @llvm.reset.fpenv()
3636
ret void
3737
}
38+
39+
define iXLen @func_get_fpmode() {
40+
; CHECK-LABEL: func_get_fpmode:
41+
; CHECK: # %bb.0: # %entry
42+
; CHECK-NEXT: frcsr a0
43+
; CHECK-NEXT: ret
44+
entry:
45+
%fpenv = call iXLen @llvm.get.fpmode.iXLen()
46+
ret iXLen %fpenv
47+
}
48+
49+
define void @func_set_fpmode(iXLen %fpmode) {
50+
; CHECK-LABEL: func_set_fpmode:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a1, -32
53+
; CHECK-NEXT: csrc fcsr, a1
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; CHECK-NEXT: andi a0, a0, -32
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; CHECK-NEXT: csrs fcsr, a0
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; CHECK-NEXT: ret
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entry:
58+
call void @llvm.set.fpmode.iXLen(iXLen %fpmode)
59+
ret void
60+
}
61+
62+
define void @func_reset_fpmode() {
63+
; CHECK-LABEL: func_reset_fpmode:
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; CHECK: # %bb.0: # %entry
65+
; CHECK-NEXT: li a0, -32
66+
; CHECK-NEXT: csrc fcsr, a0
67+
; CHECK-NEXT: ret
68+
entry:
69+
call void @llvm.reset.fpmode()
70+
ret void
71+
}

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