@@ -806,14 +806,18 @@ define i32 @main7a_logical(i32 %argc, i32 %argc2, i32 %argc3) {
806806}
807807
808808; B == (A & B) & D == (A & D)
809- define i32 @main7b (i32 %argc , i32 %argc2 , i32 %argc3 ) {
809+ define i32 @main7b (i32 %argc , i32 %argc2 , i32 %argc3x ) {
810810; CHECK-LABEL: @main7b(
811- ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
812- ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
813- ; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
814- ; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
811+ ; CHECK-NEXT: [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42
812+ ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC:%.*]], [[ARGC2:%.*]]
813+ ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
814+ ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3]], [[ARGC]]
815+ ; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]]
816+ ; CHECK-NEXT: [[AND_COND_NOT:%.*]] = or i1 [[TOBOOL]], [[TOBOOL3]]
817+ ; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32
815818; CHECK-NEXT: ret i32 [[STOREMERGE]]
816819;
820+ %argc3 = mul i32 %argc3x , 42 ; thwart complexity-based canonicalization
817821 %and1 = and i32 %argc , %argc2
818822 %tobool = icmp eq i32 %argc2 , %and1
819823 %and2 = and i32 %argc , %argc3
@@ -843,14 +847,18 @@ define i32 @main7b_logical(i32 %argc, i32 %argc2, i32 %argc3) {
843847}
844848
845849; B == (B & A) & D == (D & A)
846- define i32 @main7c (i32 %argc , i32 %argc2 , i32 %argc3 ) {
850+ define i32 @main7c (i32 %argc , i32 %argc2 , i32 %argc3x ) {
847851; CHECK-LABEL: @main7c(
848- ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[ARGC2:%.*]], [[ARGC3:%.*]]
849- ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[ARGC:%.*]]
850- ; CHECK-NEXT: [[AND_COND:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]
851- ; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND]] to i32
852+ ; CHECK-NEXT: [[ARGC3:%.*]] = mul i32 [[ARGC3X:%.*]], 42
853+ ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[ARGC2:%.*]], [[ARGC:%.*]]
854+ ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND1]], [[ARGC2]]
855+ ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[ARGC3]], [[ARGC]]
856+ ; CHECK-NEXT: [[TOBOOL3:%.*]] = icmp ne i32 [[ARGC3]], [[AND2]]
857+ ; CHECK-NEXT: [[AND_COND_NOT:%.*]] = or i1 [[TOBOOL]], [[TOBOOL3]]
858+ ; CHECK-NEXT: [[STOREMERGE:%.*]] = zext i1 [[AND_COND_NOT]] to i32
852859; CHECK-NEXT: ret i32 [[STOREMERGE]]
853860;
861+ %argc3 = mul i32 %argc3x , 42 ; thwart complexity-based canonicalization
854862 %and1 = and i32 %argc2 , %argc
855863 %tobool = icmp eq i32 %argc2 , %and1
856864 %and2 = and i32 %argc3 , %argc
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