Merge branch 'hardware'

Author: nipunaw

ftdi.py

@@ -0,0 +1,112 @@
+from pyftdi.ftdi import Ftdi
+from pyftdi.spi import (SpiController)
+from time import sleep
+
+Ftdi.show_devices()
+
+spi = SpiController()
+spi.configure('ftdi://ftdi:232h:FT4RZWM0/1')
+slave = spi.get_port(cs=0, freq = 12E4, mode=0)
+
+def writeToSlave(out: bytes):
+    global spi
+    global slave
+
+    slave.write(out)
+
+class _Getch:
+    """Gets a single character from standard input.  Does not echo to the screen."""
+    def __init__(self):
+        try:
+            self.impl = _GetchWindows()
+        except ImportError:
+            self.impl = _GetchUnix()
+
+    def __call__(self): return self.impl()
+
+
+class _GetchUnix:
+    def __init__(self):
+        import tty, sys
+
+    def __call__(self):
+        import sys, tty, termios
+        fd = sys.stdin.fileno()
+        old_settings = termios.tcgetattr(fd)
+        try:
+            tty.setraw(sys.stdin.fileno())
+            ch = sys.stdin.read(1)
+        finally:
+            termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
+        return ch
+
+
+class _GetchWindows:
+    def __init__(self):
+        import msvcrt
+
+    def __call__(self):
+        import msvcrt
+        return msvcrt.getch()
+
+
+getch = _Getch()
+
+curValue = 0
+curMode = "LED"
+
+print("Now in LED mode")
+
+while True:
+    if curMode == "LED":
+        c = ord(getch())
+
+        if c == ord('q'):
+            spi.close()
+            quit()
+        elif c == ord('t'):
+            curMode = "TAPS"
+            print("Now in Taps mode")
+            continue
+
+        n = c - ord('0')
+        a = c - ord('a')
+
+        newNibble = 0
+
+        if n in range(0, 10):
+            print(n)
+            newNibble = n
+        elif a in range(0, 7):
+            a = a + 10
+            print(a)
+            newNibble = a
+        else:
+            continue
+
+        curValue = ((curValue << 4) & 0xF0) | newNibble
+
+        writeToSlave([0x01, curValue])
+    elif curMode == "TAPS":
+        line = input()
+        
+        if line == "q":
+            spi.close()
+            quit()
+        elif line == "l":
+            curMode = "LED"
+            print("Now in LED mode")
+            continue
+
+        coefficient = int(line)
+
+        if coefficient not in range(0, 256):
+            print("Value must be between 0 and 255")
+            continue
+
+        writeToSlave([0x02, coefficient])
+
+        
+
+    
+    

public/index.html

@@ -27,4 +27,4 @@
     <noscript>You need to enable JavaScript to run this app.</noscript>
     <div id="root"></div>
   </body>
-</html>
+</html>

public/main.js

@@ -43,7 +43,6 @@ function createWindow() {
     ) {
       return true;
     }
-    return false;
   });
 
   win.webContents.session.on(
@@ -164,4 +163,4 @@ if (process.env.NODE_ENV !== "production") {
       },
     ],
   });
-}
+}

vhdl/AdderTree.vhd

@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+use work.ClariFi.all;
+
+entity AdderTree is
+    generic (
+          WIDTH : natural
+        ; NUM_OPERANDS : natural
+    );
+    port (
+          operands : in RegArray(0 to NUM_OPERANDS-1)(WIDTH-1 downto 0)
+        ; sum : out signed(WIDTH + natural(ceil(log2(real(NUM_OPERANDS)))) - 1 downto 0)
+    );
+end entity;
+
+architecture arch of AdderTree is
+    signal inner_operands : RegArray(0 to (NUM_OPERANDS / 2) + (NUM_OPERANDS mod 2) - 1)(WIDTH downto 0);
+    -- signal odd_dummy_operands : RegArray(0 to operands'high + 1)(WIDTH downto 0);
+    -- signal odd_dummy_sum : signed(sum'high downto 0);
+begin
+    -- sum <= ('0' & inner_operands(0)) + inner_operands(1);
+
+    odd_transform: if NUM_OPERANDS mod 2 = 1 generate
+        inner_operands(inner_operands'high) <= '0' & operands(operands'high);
+    end generate;
+
+    base_even: if NUM_OPERANDS = 2 generate
+        sum <= ('0' & operands(0)) + operands(1);
+    end generate;
+
+    -- base_odd: if NUM_OPERANDS = 3 generate
+    --     sum <= ('0' & (('0' & operands(0)) + operands(1))) + operands(2);
+    -- end generate;
+
+    inner_adders: if NUM_OPERANDS > 2 generate
+        recurse: for i in 0 to inner_operands'high - (NUM_OPERANDS mod 2) generate
+            inner_operands(i) <= ('0' & operands(i * 2)) + operands(i * 2 + 1);
+        end generate;
+
+        uLayerAdder: entity work.AdderTree
+            generic map (
+                  WIDTH => WIDTH + 1
+                , NUM_OPERANDS => inner_operands'length
+            )
+            port map (
+                  operands => inner_operands
+                , sum => sum
+            );
+    end generate;
+end architecture;

vhdl/BasicFIR.vhd

@@ -1,27 +1,29 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+-- library ieee;
+-- use ieee.std_logic_1164.all;
+-- use ieee.numeric_std.all;
 
-package ClariFi is
-    type CoeffiecientArray is array(natural range <>) of integer;
-    type RegArray is array(natural range <>) of signed;
-    type SLVArray is array(natural range <>) of std_logic_vector;
-end package;
+-- package ClariFi is
+--     type CoeffiecientArray is array(natural range <>) of integer;
+--     type RegArray is array(natural range <>) of signed;
+--     type SLVArray is array(natural range <>) of std_logic_vector;
+-- end package;
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use IEEE.math_real.all;
 use work.ClariFi.all;
 
 entity BasicFIR is
     generic (
           RESOLUTION : natural
         ; NUM_TAPS : natural
-        ; COEFFICIENTS : CoeffiecientArray(0 to NUM_TAPS-1)
+        -- ; COEFFICIENTS : CoeffiecientArray(0 to NUM_TAPS-1)
     );
     port (
           clk, rst, en : in std_logic
         ; sample : in std_logic_vector(RESOLUTION-1 downto 0)
+        ; coefficients : RegArray(0 to NUM_TAPS-1)
         ; filtered : out std_logic_vector(RESOLUTION-1 downto 0)
     );
 end entity;
@@ -30,7 +32,7 @@ architecture SingleOrder of BasicFIR is
     signal taps : RegArray(0 to NUM_TAPS-1)(RESOLUTION-1 downto 0);
     signal multiplies : RegArray(0 to NUM_TAPS-1)((RESOLUTION*2)-1 downto 0);
     signal multiplySLVs : SLVArray(0 to NUM_TAPS-1)((RESOLUTION*2)-1 downto 0);
-    signal accumulator : signed((RESOLUTION*2)-1 downto 0);
+    signal accumulator : signed((RESOLUTION * 2) + natural(ceil(log2(real(NUM_TAPS)))) - 1 downto 0);
 begin
     LoadTaps: process(clk, rst, en)
     begin
@@ -44,30 +46,40 @@ begin
             end loop;
         end if;
     end process;
-
+ 
     uMultipliers: for i in 0 to NUM_TAPS-1 generate
         uMultiplier: entity work.SignedMultDSP
             port map (
                   CLK => clk
                 , A => std_logic_vector(taps(i))
-                , B => std_logic_vector(to_signed(COEFFICIENTS(i), RESOLUTION))
+                , B => std_logic_vector(COEFFICIENTS(i))
                 , P => multiplySLVs(i)
             );
 
         multiplies(i) <= signed(multiplySLVs(i));
     end generate;
 
-    process (multiplies)
-        variable acc : signed(accumulator'range) := (others => '0');
-    begin
-        acc := (others => '0');
+    -- proc_accumulator: process (multiplies)
+    --     variable acc : signed(accumulator'range) := (others => '0');
+    -- begin
+    --     acc := (others => '0');
 
-        for i in 0 to NUM_TAPS-1 loop
-            acc := acc + multiplies(i);
-        end loop;
+    --     for i in 0 to NUM_TAPS-1 loop
+    --         acc := acc + multiplies(i);
+    --     end loop;
 
-        accumulator <= acc;
-    end process;
+    --     accumulator <= acc;
+    -- end process;
+
+    uAdderTree: entity work.AdderTree
+        generic map (
+              WIDTH => RESOLUTION*2
+            , NUM_OPERANDS => NUM_TAPS
+        )
+        port map (
+              operands => multiplies
+            , sum => accumulator
+        );
 
     filtered <= std_logic_vector(accumulator(accumulator'high downto accumulator'high - (RESOLUTION - 1)));
 end architecture;

vhdl/CS4272.vhd

@@ -0,0 +1,95 @@
+-- Controller for the CS4272-DZZ (DAC and ADC)
+-- Assuming a sample frequency of 44.1 kHz
+-- Note that unless we have Fs > 50 KHz, pins M0 and M1 
+-- should both be 0 (can just connect to DGND).
+-- CTRL = x"10" & RegAddr & Data
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity CS4272 is
+    generic (
+        WIDTH : natural
+    );
+    port (
+        clk : in std_logic;
+        rst : in std_logic;
+        --go  : in std_logic;
+        en  : in std_logic;
+        DIN : in std_logic_vector(WIDTH-1 downto 0); -- Digital in
+        AIN : in std_logic_vector(WIDTH-1 downto 0); -- Analog in
+        CS  : out std_logic; -- Connect to pin 13
+        DOUT : out std_logic_vector(WIDTH-1 downto 0);
+        AOUT : out std_logic_vector(WIDTH-1 downto 0);
+        CTRL : out std_logic_vector(23 downto 0); -- Control signal for configuration
+        converting : out std_logic;
+        done : out std_logic
+    );
+end entity;
+
+architecture ADC_DAC of CS4272 is
+
+    type StateType is (S_Ready, S_DACControl, S_Converting, S_Done);
+    signal state_r, next_state : StateType;
+    signal ADC_data_r, DAC_data_r : std_logic_vector(WIDTH-1 downto 0);
+
+begin
+    process (clk, rst)
+    begin
+        if (rst = '1') then 
+            state_r <= S_Ready;
+            ADC_data_r <= (others => '0');
+            DAC_data_r <= (others => '0');
+        elsif (rising_edge(clk)) then 
+            state_r <= next_state;
+        end if;
+    end process;
+
+    AIN <= ADC_data_r;
+    DIN <= DAC_data_r;
+
+    process (state_r, go, en, DIN, AIN)
+    begin 
+        done <= '0';
+        converting <= '0';
+        next_state <= state_r;  
+
+        case state_r is         
+            when S_Ready => 
+                CS <= '0';
+                CTRL <= x"10" & x"07" & x"02"; -- Chip address, write, set CPEN, clear PDN
+                next_state <= S_DACControl; -- we should always do configuration first regardless of go
+
+            when S_DACControl =>
+                CS <= '0';
+                -- Auto-Mute off, fast roll off, De-Emphasis Filter off, Ramp-up/down off, no inversion
+                -- The default is x"00" anyways but in case we want to enable any option later
+                CTRL <= x"10" & x"02" & x"00"; 
+                next_state <= S_ADCControl;
+
+            when S_ADCControl => 
+                CS <= '0';
+                -- Dither16 is off (when we're using 8-bits resolution), 24-bit LJ, No mutes, High pass filter enabled (default)
+                CTRL <= x"10" & x"06" & x"00";
+                if (en = '1') -- when do we start converting 
+                    next_state <= S_Converting;
+                end if;
+
+            when S_Converting => 
+                CS <= '1';
+                converting <= '1';
+                ADC_data_r <= AIN; -- Connect pins appropriately 
+                DAC_data_r <= DIN;
+                next_state <= S_Done;
+
+            when S_Done => 
+                CS <= '1';
+                done <= '1'; -- you can get the data now
+                if (en = '1')
+                    done <= '0'; -- another conversion 
+                    next_state <= S_Converting; -- just convert, registers are already configured
+                end if;
+        end case;
+    end process;
+end architecture;