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FPGA and software crossover to bring your microphone clarity and fidelity
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**[Time Logs]**
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Time logging notes beyond git commits are available in **resources/**.
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**[Hardware]**
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VHDL files included in 'vhdl' folder. Schematic files included in 'schematics' folder.
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**[Software]**
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Dependencies:
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Current development is done on Windows and the main target platform is Windows. This application is built using ElectronJS and ReactJS
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Note: When installing packages, a warning will appear about npm package vulnerabilities. This is not a concern and is addressed here: https://github.com/facebook/create-react-app/issues/11174
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**[Hardware]**
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VHDL files included in 'vhdl' folder. Schematic files included in 'schematics' folder.
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Synthesizing steps:
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The HDL is synthesized by the Vivado 2021.1 build system. It has not been tested on other versions of Vivado.
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1. Download the Vivado project zip file from the Releases tab.
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2. Unzip the archive and open the project in Vivado
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3. Double click on "Generate Bitstream" to generate the bitstream for the Arty A7-35 (xc7a35ticsg324-1L) FPGA, which is preconfigured. Other devices may be selected, however neither performance nor compatibility are guaranteed.
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The default pinout, which can also be found in the constraint file, is:
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