@@ -101,6 +101,8 @@ class MergeInputSpec(DynamicTraitedSpec, BaseInterfaceInputSpec):
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desc = 'direction in which to merge, hstack requires same number of elements in each input' )
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no_flatten = traits .Bool (False , usedefault = True ,
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desc = 'append to outlist instead of extending in vstack mode' )
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+ ravel_inputs = traits .Bool (False , usedefault = True ,
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+ desc = 'ravel inputs with no_flatten is False' )
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class MergeOutputSpec (TraitedSpec ):
@@ -141,6 +143,13 @@ class Merge(IOBase):
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>>> merge.inputs.in1 = [1, [2, 5], 3]
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>>> out = merge.run()
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>>> out.outputs.out
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+ [1, [2, 5], 3]
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+
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+ >>> merge = Merge() # Or Merge(1)
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+ >>> merge.inputs.in1 = [1, [2, 5], 3]
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+ >>> merge.inputs.ravel_inputs = True
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+ >>> out = merge.run()
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+ >>> out.outputs.out
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[1, 2, 5, 3]
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>>> merge = Merge() # Or Merge(1)
@@ -176,7 +185,10 @@ def _list_outputs(self):
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if self .inputs .axis == 'vstack' :
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for value in values :
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if isinstance (value , list ) and not self .inputs .no_flatten :
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- out .extend (_ravel (value ))
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+ if self .inputs .ravel_inputs :
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+ out .extend (_ravel (value ))
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+ else :
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+ out .extend (value )
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else :
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out .append (value )
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else :
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