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| 1 | +// RUN: iree-opt --amdaie-create-pathfinder-flows %s | FileCheck %s |
| 2 | + |
| 3 | +// Routing test for three packet flows from memtile (0,1) to coretile (0,2). |
| 4 | +// Two of the flows target the same destination port, configured as out-of-order mode. |
| 5 | + |
| 6 | +// CHECK-LABEL: aie.device(npu1_4col) { |
| 7 | +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) |
| 8 | +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { |
| 9 | +// CHECK: %[[AMSEL_0:.*]] = aie.amsel<0> (0) |
| 10 | +// CHECK: %[[AMSEL_1:.*]] = aie.amsel<1> (0) |
| 11 | +// CHECK: %[[MASTERSET_NORTH_0:.*]] = aie.masterset(NORTH : 0, %[[AMSEL_0]]) |
| 12 | +// CHECK: %[[MASTERSET_NORTH_5:.*]] = aie.masterset(NORTH : 5, %[[AMSEL_1]]) |
| 13 | +// CHECK: aie.packet_rules(DMA : 1) { |
| 14 | +// CHECK: aie.rule(31, 0, %[[AMSEL_0]]) {packet_ids = array<i32: 0>} |
| 15 | +// CHECK: } |
| 16 | +// CHECK: aie.packet_rules(DMA : 2) { |
| 17 | +// CHECK: aie.rule(31, 0, %[[AMSEL_1]]) {packet_ids = array<i32: 0>} |
| 18 | +// CHECK: } |
| 19 | +// CHECK: aie.packet_rules(DMA : 3) { |
| 20 | +// CHECK: aie.rule(31, 0, %[[AMSEL_0]]) {packet_ids = array<i32: 0>} |
| 21 | +// CHECK: } |
| 22 | +// CHECK: } |
| 23 | +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) |
| 24 | +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { |
| 25 | +// CHECK: %[[AMSEL_0:.*]] = aie.amsel<0> (0) |
| 26 | +// CHECK: %[[AMSEL_1:.*]] = aie.amsel<1> (0) |
| 27 | +// CHECK: %[[MASTERSET_DMA_0:.*]] = aie.masterset(DMA : 0, %[[AMSEL_0]]) {keep_pkt_header = "true"} |
| 28 | +// CHECK: %[[MASTERSET_DMA_1:.*]] = aie.masterset(DMA : 1, %[[AMSEL_1]]) |
| 29 | +// CHECK: aie.packet_rules(SOUTH : 0) { |
| 30 | +// CHECK: aie.rule(31, 0, %[[AMSEL_0]]) {packet_ids = array<i32: 0>} |
| 31 | +// CHECK: } |
| 32 | +// CHECK: aie.packet_rules(SOUTH : 5) { |
| 33 | +// CHECK: aie.rule(31, 0, %[[AMSEL_1]]) {packet_ids = array<i32: 0>} |
| 34 | +// CHECK: } |
| 35 | +// CHECK: } |
| 36 | +// CHECK: } |
| 37 | +module { |
| 38 | + aie.device(npu1_4col) { |
| 39 | + %tile_0_1 = aie.tile(0, 1) |
| 40 | + %tile_0_2 = aie.tile(0, 2) |
| 41 | + aie.packet_flow(0) { |
| 42 | + aie.packet_source<%tile_0_1, DMA : 1> |
| 43 | + aie.packet_dest<%tile_0_2, DMA : 0> |
| 44 | + } {keep_pkt_header = true} |
| 45 | + aie.packet_flow(0) { |
| 46 | + aie.packet_source<%tile_0_1, DMA : 2> |
| 47 | + aie.packet_dest<%tile_0_2, DMA : 1> |
| 48 | + } |
| 49 | + aie.packet_flow(0) { |
| 50 | + aie.packet_source<%tile_0_1, DMA : 3> |
| 51 | + aie.packet_dest<%tile_0_2, DMA : 0> |
| 52 | + } {keep_pkt_header = true} |
| 53 | + } |
| 54 | +} |
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