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Yu-ZhewenYu-Zhewen
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[MatmulThinBias] Enable out-of-order DMA mode (#1341)
MatmulThinBias was previously only supported through the AIR pipeline, not the ObjectFifo pipeline. The main challenge is that each core requires three input tensors, while the hardware provides only two DMA S2MM (input) channels. In the AIR pipeline, this limitation was addressed by concatenating the bias tensor with another input to reduce channel usage. This PR introduces support for the ObjectFifo pipeline by leveraging out-of-order DMA mode instead, which allows multiple MM2S channels to feed data into a single S2MM channel. When an MM2S channel sends data, it embeds the corresponding BD ID, which it wants the destination S2MM to trigger, directly into the packet header of the data stream. A single-core example has been added to the CI. Support for larger shapes and MatmulFullBias is still blocked at the ObjFifoSplitting stage and will be addressed in follow-up PRs.
1 parent 2d9807d commit 5b4c9c5

32 files changed

+835
-283
lines changed

‎build_tools/ci/cpu_comparison/run.py‎

Lines changed: 57 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -538,11 +538,7 @@ def __init__(
538538
super().__init__(
539539
name=f"matmul_thin_bias_{M}_{N}_{K}_{input_type}_{acc_type}",
540540
function_name="matmul_bias",
541-
test_params=(
542-
test_params
543-
if test_params is not None
544-
else TestParams(lower_to_aie_pipeline="air", enable_ctrlpkt=False)
545-
),
541+
test_params=test_params,
546542
M=M,
547543
N=N,
548544
K=K,
@@ -551,13 +547,7 @@ def __init__(
551547
)
552548
self.labels.append("MatmulThinBias")
553549

554-
self.add_aie_compilation_flags(
555-
[
556-
"--iree-amdaie-matmul-elementwise-fusion",
557-
"--iree-amdaie-num-rows=2",
558-
"--iree-amdaie-num-cols=2",
559-
]
560-
)
550+
self.add_aie_compilation_flags(["--iree-amdaie-matmul-elementwise-fusion"])
561551

562552
def generate(self, config):
563553
template_name = (
@@ -583,11 +573,7 @@ def __init__(
583573
super().__init__(
584574
name=f"matmul_full_bias_{M}_{N}_{K}_{input_type}_{acc_type}",
585575
function_name="matmul_bias",
586-
test_params=(
587-
test_params
588-
if test_params is not None
589-
else TestParams(lower_to_aie_pipeline="air", enable_ctrlpkt=False)
590-
),
576+
test_params=test_params,
591577
M=M,
592578
N=N,
593579
K=K,
@@ -596,13 +582,7 @@ def __init__(
596582
)
597583
self.labels.append("MatmulFullBias")
598584

599-
self.add_aie_compilation_flags(
600-
[
601-
"--iree-amdaie-matmul-elementwise-fusion",
602-
"--iree-amdaie-num-rows=2",
603-
"--iree-amdaie-num-cols=2",
604-
]
605-
)
585+
self.add_aie_compilation_flags(["--iree-amdaie-matmul-elementwise-fusion"])
606586

607587
def generate(self, config):
608588
template_name = (
@@ -1829,10 +1809,61 @@ def __init__(self):
18291809
)
18301810

18311811
# MatmulThinBias test(s):
1832-
self.register(MatmulThinBias(1024, 1024, 512, "bf16", "f32"))
1812+
self.register(
1813+
MatmulThinBias(
1814+
1024,
1815+
1024,
1816+
512,
1817+
"bf16",
1818+
"f32",
1819+
test_params=TestParams(
1820+
lower_to_aie_pipeline="air",
1821+
enable_ctrlpkt=False,
1822+
aie_compilation_flags=[
1823+
"--iree-amdaie-num-rows=2",
1824+
"--iree-amdaie-num-cols=2",
1825+
],
1826+
),
1827+
)
1828+
)
1829+
# Use objfifo lowering with out-of-order DMA mode.
1830+
self.register(
1831+
MatmulThinBias(
1832+
32,
1833+
32,
1834+
32,
1835+
"bf16",
1836+
"f32",
1837+
test_params=TestParams(
1838+
enable_ctrlpkt=False,
1839+
aie_compilation_flags=[
1840+
"--iree-amdaie-num-rows=1",
1841+
"--iree-amdaie-num-cols=1",
1842+
"--iree-amdaie-reprogram-dmas=true",
1843+
"--iree-amdaie-packet-flow-strategy=inputs",
1844+
],
1845+
),
1846+
)
1847+
)
18331848

18341849
# MatmulFullBias test:
1835-
self.register(MatmulFullBias(128, 128, 256, "bf16", "f32"))
1850+
self.register(
1851+
MatmulFullBias(
1852+
128,
1853+
128,
1854+
256,
1855+
"bf16",
1856+
"f32",
1857+
test_params=TestParams(
1858+
lower_to_aie_pipeline="air",
1859+
enable_ctrlpkt=False,
1860+
aie_compilation_flags=[
1861+
"--iree-amdaie-num-rows=2",
1862+
"--iree-amdaie-num-cols=2",
1863+
],
1864+
),
1865+
)
1866+
)
18361867

18371868
# MatmulTransposeB test(s):
18381869
for input_type, acc_type in zip(["i8", "bf16"], ["i32", "f32"]):

‎compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,11 +61,11 @@ LogicalResult appendWriteBd(xilinx::AIEX::NpuWriteBdOp op,
6161
if (failed(transactionBuilder.appendWriteBdOp(
6262
op.getColumn(), op.getRow(), op.getBdId(), op.getBufferLength(),
6363
op.getBufferOffset(), op.getEnablePacket(), op.getPacketId(),
64-
op.getPacketType(), sizes, strides, op.getIterationCurrent(),
65-
op.getIterationSize(), op.getIterationStride(), op.getNextBd(),
66-
op.getUseNextBd(), op.getValidBd(), op.getLockRelVal(),
67-
op.getLockRelId(), op.getLockAcqEnable(), op.getLockAcqVal(),
68-
op.getLockAcqId()))) {
64+
op.getPacketType(), op.getOutOfOrderId(), sizes, strides,
65+
op.getIterationCurrent(), op.getIterationSize(),
66+
op.getIterationStride(), op.getNextBd(), op.getUseNextBd(),
67+
op.getValidBd(), op.getLockRelVal(), op.getLockRelId(),
68+
op.getLockAcqEnable(), op.getLockAcqVal(), op.getLockAcqId()))) {
6969
return failure();
7070
}
7171
return success();

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/AMDAIEOps.td‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1762,7 +1762,8 @@ def AMDAIE_DMAStartOp: AMDAIE_Op<"dma_start", [
17621762
ins Index:$channel,
17631763
Variadic<Index>:$connections,
17641764
// `repeat_count==1` means "do it once".
1765-
DefaultValuedAttr<I8Attr, "1">:$repeat_count
1765+
DefaultValuedAttr<I8Attr, "1">:$repeat_count,
1766+
OptionalAttr<BoolAttr>:$enable_out_of_order
17661767
);
17671768
let regions = (region AnyRegion:$body);
17681769
let assemblyFormat = [{
@@ -1774,6 +1775,23 @@ def AMDAIE_DMAStartOp: AMDAIE_Op<"dma_start", [
17741775
}];
17751776
}
17761777

1778+
1779+
def AMDAIE_DmaBdPacketOp: AMDAIE_Op<"dma_bd_packet"> {
1780+
let summary = "Enable packet headers for a dma block descriptor";
1781+
let description = [{
1782+
This operation defines the packet metadata, including `packet_type`, `packet_id`,
1783+
and `out_of_order_bd_id`, which will be inserted into the packet header associated
1784+
with this DMA BD.
1785+
}];
1786+
let arguments = (
1787+
ins I32Attr:$packet_type,
1788+
I32Attr:$packet_id,
1789+
OptionalAttr<I32Attr>:$out_of_order_bd_id
1790+
);
1791+
1792+
let assemblyFormat = [{ attr-dict }];
1793+
}
1794+
17771795
def AMDAIE_DMABDOp: AMDAIE_Op<"dma_bd", [
17781796
DeclareOpInterfaceMethods<OpAsmOpInterface>
17791797
]> {

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/IR/test/roundtrip.mlir‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -684,13 +684,14 @@ func.func @from_memref_unknown_row_column(%arg0 : memref<8xi32>, %t0 : index) {
684684
// CHECK: %[[CONNECTION:.*]] = amdaie.connection
685685
// CHECK: amdaie.dma_start(%[[CHANNEL]], {%[[CONNECTION]]}) {
686686
// CHECK: amdaie.use_lock(%[[LOCK_0]], AcquireGreaterOrEqual(1))
687+
// CHECK: amdaie.dma_bd_packet {out_of_order_bd_id = 0 : i32, packet_id = 1 : i32, packet_type = 2 : i32}
687688
// CHECK: amdaie.dma_bd(%[[BUFFER]] : memref<1024xi32, 2 : i32>)
688689
// CHECK-SAME: {dimensions = #amdaie<bd_dim_layout_array[<size = 32, stride = 8>, <size = 4, stride = 256>, <size = 8, stride = 1>]>, len = 1024 : i32}
689690
// CHECK: amdaie.use_lock(%[[LOCK_1]], Release(1))
690691
// CHECK: amdaie.next_bd ^bb1
691-
// CHECK: ^bb1:
692+
// CHECK: ^bb1:
692693
// CHECK: amdaie.end
693-
// CHECK: }
694+
// CHECK: } {enable_out_of_order = true, repeat_count = 2 : i8}
694695
func.func @dma_start_block_ops(%arg0: !amdaie.logicalobjectfifo<memref<1024xi32, 1 : i32>>, %arg1: !amdaie.logicalobjectfifo<memref<1024xi32, 2 : i32>>) {
695696
%c0 = arith.constant 0 : index
696697
%c2 = arith.constant 2 : index
@@ -702,11 +703,12 @@ func.func @dma_start_block_ops(%arg0: !amdaie.logicalobjectfifo<memref<1024xi32,
702703
%connection = amdaie.connection(%arg0, %arg1 {%channel}) : (!amdaie.logicalobjectfifo<memref<1024xi32, 1 : i32>>, !amdaie.logicalobjectfifo<memref<1024xi32, 2 : i32>>)
703704
amdaie.dma_start(%channel, {%connection}) {
704705
amdaie.use_lock(%lock, AcquireGreaterOrEqual(1))
706+
amdaie.dma_bd_packet {out_of_order_bd_id = 0 : i32, packet_id = 1 : i32, packet_type = 2 : i32}
705707
amdaie.dma_bd(%buffer : memref<1024xi32, 2 : i32>) {dimensions = #amdaie<bd_dim_layout_array[<size = 32, stride = 8>, <size = 4, stride = 256>, <size = 8, stride = 1>]>, len = 1024 : i32}
706708
amdaie.use_lock(%lock_0, Release(1))
707709
amdaie.next_bd ^bb1
708710
^bb1: // pred: ^bb0
709711
amdaie.end
710-
}
712+
} {enable_out_of_order = true, repeat_count = 2 : i8}
711713
return
712714
}

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/AMDAIERT.cpp‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -234,6 +234,7 @@ LogicalResult configureLocksAndBd(Block &block, const TileLoc &tileLoc,
234234
if (failed(configureDMABD(deviceModel, dmaTileBd.value(), tileLoc, validBd,
235235
static_cast<uint8_t>(*bdOp.getBdId()), enableNextBd,
236236
nextBdId, enablePacket, packetType, packetID,
237+
/*outOfOrderBdId=*/std::nullopt,
237238
*bufferOp.getAddress(), getLenInBytes(bdOp),
238239
getOffsetInBytes(bdOp),
239240
getBufferElementTypeWidthInBytes(bdOp), maybeDims,
@@ -298,9 +299,12 @@ LogicalResult addInitConfig(const AMDAIEDeviceModel &deviceModel,
298299
int chNum = op.getChannelIndex();
299300
auto channelDir = static_cast<DMAChannelDir>(op.getChannelDir());
300301
bool issueToken = tileLoc.row == 0 && channelDir == DMAChannelDir::MM2S;
301-
if (failed(configurePushToBdQueue(deviceModel, tileLoc, chNum,
302-
channelDir, bd.getBdId().value(),
303-
op.getRepeatCount(), issueToken)))
302+
// TODO(zhewen): Currently, out-of-order mode can only be configured via
303+
// the AMDAIE dialect. Support through the AIE dialect needs to be
304+
// implemented.
305+
if (failed(configurePushToBdQueue(
306+
deviceModel, tileLoc, chNum, channelDir, bd.getBdId().value(),
307+
op.getRepeatCount(), issueToken, /*enableOutOfOrder=*/false)))
304308
return failure();
305309
}
306310
}

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/test/add_12_i8_using_2d_dma_op_with_padding.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ module {
3838
// CHECK: XAIE API: XAie_DmaSetNextBd with args: &dmaDesc=ptr, nextBdId.value()=0, enableNextBd=1
3939
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
4040
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 1), bdId=0
41-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
41+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
4242

4343
// CHECK: cdo-driver: (NOP Command): Payload Length: 0
4444

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/test/add_21_i8_using_dma_op_with_padding.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ module {
5050
// CHECK: XAIE API: XAie_DmaSetPadding with args: &dmaDesc=ptr, &dmaPadTensor=ptr
5151
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
5252
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 1), bdId=1
53-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
53+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
5454

5555
// CHECK: cdo-driver: (NOP Command): Payload Length: 0
5656

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/test/add_378_i32_using_dma_op_with_padding.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ module {
4949
// CHECK: XAIE API: XAie_DmaSetPadding with args: &dmaDesc=ptr, &dmaPadTensor=ptr
5050
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
5151
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 1), bdId=1
52-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
52+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
5353

5454
// CHECK: cdo-driver: (NOP Command): Payload Length: 0
5555

‎compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/test/bd_chaining.mlir‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -240,9 +240,9 @@ aie.device(npu1_4col) {
240240
// CHECK: XAIE API: XAie_DmaSetNextBd with args: &dmaDesc=ptr, nextBdId.value()=3, enableNextBd=1
241241
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
242242
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 2), bdId=6
243-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
244-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=1, direction=0, bdId=1, repeatCount=1, enTokenIssue=0
245-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=0, direction=1, bdId=3, repeatCount=1, enTokenIssue=0
243+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=0, direction=0, &dmaQueueDesc=ptr
244+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=1, direction=0, &dmaQueueDesc=ptr
245+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 2), chNum=0, direction=1, &dmaQueueDesc=ptr
246246
// CHECK: XAIE API: XAie_DmaDescInit with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 2, row: 1)
247247
// CHECK: XAIE API: dmaDesc.DmaMod->SetLock with args: &dmaDesc=ptr, acqLock=XAie_Lock(LockId: 65, LockVal: -1), relLock=XAie_Lock(LockId: 64, LockVal: 1), acqEn=1, relEn=0
248248
// CHECK: XAIE API: XAie_DmaSetAddrLen with args: &dmaDesc=ptr, basePlusOffsetInBytes=524288, lenInBytes=1024
@@ -255,8 +255,8 @@ aie.device(npu1_4col) {
255255
// CHECK: XAIE API: XAie_DmaSetNextBd with args: &dmaDesc=ptr, nextBdId.value()=1, enableNextBd=1
256256
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
257257
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 2, row: 1), bdId=1
258-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 2, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
259-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 2, row: 1), chNum=0, direction=1, bdId=1, repeatCount=1, enTokenIssue=0
258+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 2, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
259+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 2, row: 1), chNum=0, direction=1, &dmaQueueDesc=ptr
260260
// CHECK: XAIE API: XAie_DmaDescInit with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 1)
261261
// CHECK: XAIE API: dmaDesc.DmaMod->SetLock with args: &dmaDesc=ptr, acqLock=XAie_Lock(LockId: 65, LockVal: -1), relLock=XAie_Lock(LockId: 64, LockVal: 1), acqEn=1, relEn=0
262262
// CHECK: XAIE API: XAie_DmaSetAddrLen with args: &dmaDesc=ptr, basePlusOffsetInBytes=524288, lenInBytes=512
@@ -270,8 +270,8 @@ aie.device(npu1_4col) {
270270
// CHECK: XAIE API: XAie_DmaSetNextBd with args: &dmaDesc=ptr, nextBdId.value()=1, enableNextBd=1
271271
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
272272
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 0, row: 1), bdId=1
273-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
274-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=1, bdId=1, repeatCount=1, enTokenIssue=0
273+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
274+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 1), chNum=0, direction=1, &dmaQueueDesc=ptr
275275
// CHECK: XAIE API: XAie_DmaDescInit with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 1, row: 1)
276276
// CHECK: XAIE API: dmaDesc.DmaMod->SetLock with args: &dmaDesc=ptr, acqLock=XAie_Lock(LockId: 65, LockVal: -1), relLock=XAie_Lock(LockId: 64, LockVal: 1), acqEn=1, relEn=0
277277
// CHECK: XAIE API: XAie_DmaSetAddrLen with args: &dmaDesc=ptr, basePlusOffsetInBytes=524288, lenInBytes=2048
@@ -285,8 +285,8 @@ aie.device(npu1_4col) {
285285
// CHECK: XAIE API: XAie_DmaSetNextBd with args: &dmaDesc=ptr, nextBdId.value()=1, enableNextBd=1
286286
// CHECK: XAIE API: XAie_DmaEnableBd with args: &dmaDesc=ptr
287287
// CHECK: XAIE API: XAie_DmaWriteBd with args: devInst=ptr, &dmaDesc=ptr, tileLoc=TileLoc(col: 1, row: 1), bdId=1
288-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 1, row: 1), chNum=0, direction=0, bdId=0, repeatCount=1, enTokenIssue=0
289-
// CHECK: XAIE API: XAie_DmaChannelSetStartQueue with args: devInst=ptr, tileLoc=TileLoc(col: 1, row: 1), chNum=0, direction=1, bdId=1, repeatCount=1, enTokenIssue=0
288+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 1, row: 1), chNum=0, direction=0, &dmaQueueDesc=ptr
289+
// CHECK: XAIE API: XAie_DmaChannelSetStartQueueGeneric with args: devInst=ptr, tileLoc=TileLoc(col: 1, row: 1), chNum=0, direction=1, &dmaQueueDesc=ptr
290290
// CHECK: XAIE API: XAie_StrmConnCctEnable with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 0), CTRL=StrmSwPortType::CTRL, slvPortNum=0, SOUTH=StrmSwPortType::SOUTH, mstrPortNum=0
291291
// CHECK: XAIE API: XAie_StrmConnCctEnable with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 0), strmTtoStrmT(connect.src.bundle)=StrmSwPortType::SOUTH, connect.src.channel=3, strmTtoStrmT(connect.dst.bundle)=StrmSwPortType::NORTH, connect.dst.channel=0
292292
// CHECK: XAIE API: XAie_StrmConnCctEnable with args: devInst=ptr, tileLoc=TileLoc(col: 0, row: 0), strmTtoStrmT(connect.src.bundle)=StrmSwPortType::SOUTH, connect.src.channel=7, strmTtoStrmT(connect.dst.bundle)=StrmSwPortType::EAST, connect.dst.channel=0

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