[X86][StrictFP] Add widening support for STRICT_FMIN/STRICT_FMAX (llvm#119391)

Fixes: llvm#119422

Author: phoebewang

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -33424,15 +33424,26 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
   case X86ISD::FMINC:
   case X86ISD::FMIN:
   case X86ISD::FMAXC:
-  case X86ISD::FMAX: {
+  case X86ISD::FMAX:
+  case X86ISD::STRICT_FMIN:
+  case X86ISD::STRICT_FMAX: {
     EVT VT = N->getValueType(0);
     assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
+    bool IsStrict = Opc == X86ISD::STRICT_FMIN || Opc == X86ISD::STRICT_FMAX;
     SDValue UNDEF = DAG.getUNDEF(VT);
     SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
-                              N->getOperand(0), UNDEF);
+                              N->getOperand(IsStrict ? 1 : 0), UNDEF);
     SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
-                              N->getOperand(1), UNDEF);
-    Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
+                              N->getOperand(IsStrict ? 2 : 1), UNDEF);
+    SDValue Res;
+    if (IsStrict)
+      Res = DAG.getNode(Opc, dl, {MVT::v4f32, MVT::Other},
+                        {N->getOperand(0), LHS, RHS});
+    else
+      Res = DAG.getNode(Opc, dl, MVT::v4f32, LHS, RHS);
+    Results.push_back(Res);
+    if (IsStrict)
+      Results.push_back(Res.getValue(1));
     return;
   }
   case ISD::SDIV:

llvm/test/CodeGen/X86/vec-strict-cmp-128.ll

@@ -6087,9 +6087,106 @@ define <2 x double> @test_v4f64_ogt2_s(<2 x double> %a, <2 x double> %b) #0 {
   ret <2 x double> %res
 }
 
+define <2 x float> @test_v2f32_ogt2_s(<2 x float> %a, <2 x float> %b) #0 {
+; SSE-32-LABEL: test_v2f32_ogt2_s:
+; SSE-32:       # %bb.0:
+; SSE-32-NEXT:    maxps %xmm1, %xmm0
+; SSE-32-NEXT:    retl
+;
+; SSE-64-LABEL: test_v2f32_ogt2_s:
+; SSE-64:       # %bb.0:
+; SSE-64-NEXT:    maxps %xmm1, %xmm0
+; SSE-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_v2f32_ogt2_s:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_v2f32_ogt2_s:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX-64-NEXT:    retq
+;
+; AVX512-32-LABEL: test_v2f32_ogt2_s:
+; AVX512-32:       # %bb.0:
+; AVX512-32-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX512-32-NEXT:    retl
+;
+; AVX512-64-LABEL: test_v2f32_ogt2_s:
+; AVX512-64:       # %bb.0:
+; AVX512-64-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX512-64-NEXT:    retq
+;
+; AVX512F-32-LABEL: test_v2f32_ogt2_s:
+; AVX512F-32:       # %bb.0:
+; AVX512F-32-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX512F-32-NEXT:    retl
+;
+; AVX512F-64-LABEL: test_v2f32_ogt2_s:
+; AVX512F-64:       # %bb.0:
+; AVX512F-64-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX512F-64-NEXT:    retq
+  %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(
+                                               <2 x float> %a, <2 x float> %b, metadata !"ogt",
+                                               metadata !"fpexcept.strict")
+  %res = select <2 x i1> %cond, <2 x float> %a, <2 x float> %b
+  ret <2 x float> %res
+}
+
+define <2 x float> @test_v2f32_ule2_s(<2 x float> %a, <2 x float> %b) #0 {
+; SSE-32-LABEL: test_v2f32_ule2_s:
+; SSE-32:       # %bb.0:
+; SSE-32-NEXT:    minps %xmm0, %xmm1
+; SSE-32-NEXT:    movaps %xmm1, %xmm0
+; SSE-32-NEXT:    retl
+;
+; SSE-64-LABEL: test_v2f32_ule2_s:
+; SSE-64:       # %bb.0:
+; SSE-64-NEXT:    minps %xmm0, %xmm1
+; SSE-64-NEXT:    movaps %xmm1, %xmm0
+; SSE-64-NEXT:    retq
+;
+; AVX-32-LABEL: test_v2f32_ule2_s:
+; AVX-32:       # %bb.0:
+; AVX-32-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX-32-NEXT:    retl
+;
+; AVX-64-LABEL: test_v2f32_ule2_s:
+; AVX-64:       # %bb.0:
+; AVX-64-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX-64-NEXT:    retq
+;
+; AVX512-32-LABEL: test_v2f32_ule2_s:
+; AVX512-32:       # %bb.0:
+; AVX512-32-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX512-32-NEXT:    retl
+;
+; AVX512-64-LABEL: test_v2f32_ule2_s:
+; AVX512-64:       # %bb.0:
+; AVX512-64-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX512-64-NEXT:    retq
+;
+; AVX512F-32-LABEL: test_v2f32_ule2_s:
+; AVX512F-32:       # %bb.0:
+; AVX512F-32-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX512F-32-NEXT:    retl
+;
+; AVX512F-64-LABEL: test_v2f32_ule2_s:
+; AVX512F-64:       # %bb.0:
+; AVX512F-64-NEXT:    vminps %xmm0, %xmm1, %xmm0
+; AVX512F-64-NEXT:    retq
+  %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(
+                                               <2 x float> %a, <2 x float> %b, metadata !"ule",
+                                               metadata !"fpexcept.strict")
+  %res = select <2 x i1> %cond, <2 x float> %a, <2 x float> %b
+  ret <2 x float> %res
+}
+
 attributes #0 = { strictfp nounwind }
 
 declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float>, <4 x float>, metadata, metadata)
 declare <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double>, <2 x double>, metadata, metadata)
+declare <2 x i1> @llvm.experimental.constrained.fcmps.v2f32(<2 x float>, <2 x float>, metadata, metadata)
 declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float>, <4 x float>, metadata, metadata)
 declare <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double>, <2 x double>, metadata, metadata)