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Fix error handling in spihal and debugenabled/mmconfig modules
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1 parent 8e3c0c9 commit 19b3837

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3 files changed

+11
-1
lines changed

3 files changed

+11
-1
lines changed

chipsec/hal/intel/spi.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
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from chipsec.library.logger import print_buffer_bytes
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from chipsec.hal import hal_base
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from chipsec.library.spi_jedec_ids import JEDEC_ID
54-
from chipsec.library.exceptions import SpiRuntimeError
54+
from chipsec.library.exceptions import SpiRuntimeError, HALInitializationError
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from chipsec.library.intel.spi import SPI_REGION, SPI_FLA_SHIFT, SPI_FLA_PAGE_MASK, SPI_REGION_NAMES, SPI_REGION_tuple, print_SPI_Flash_Regions
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5757
SPI_READ_WRITE_MAX_DBC = 64

chipsec/modules/common/debugenabled.py

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,9 @@ def check_dci(self) -> int:
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self.logger.log('')
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self.logger.log('[*] Checking DCI register status')
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ectrl = self.cs.register.get_list_by_name('ECTRL')
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if not ectrl:
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self.logger.log_important('ECTRL register not found. Skipping DCI check.')
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return ModuleResult.WARNING
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ectrl.read_and_verbose_print()
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hdcien_mask = ectrl[0].get_field_mask('ENABLE', True)
8285

@@ -95,6 +98,9 @@ def check_cpu_debug_enable(self) -> int:
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self.logger.log('[*] Checking IA32_DEBUG_INTERFACE MSR status')
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TestFail = ModuleResult.PASSED
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dbg_regs = self.cs.register.get_list_by_name('IA32_DEBUG_INTERFACE')
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if not dbg_regs:
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self.logger.log_important('IA32_DEBUG_INTERFACE MSR not found. Skipping CPU debug enable check.')
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return ModuleResult.WARNING
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dbg_regs.read_and_verbose_print()
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chipsec/modules/common/memconfig.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,10 @@ def check_memmap_locks(self) -> int:
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self.logger.log_important(f'{reg}.{self.memmap_registers[reg]} not defined for platform. Skipping register.')
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continue
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reglist = self.cs.register.get_list_by_name(reg)
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if not reglist:
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all_locked = False
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self.logger.log_important(f'{reg} register not found. Unable to verify lock state.')
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continue
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description = reglist[0].desc
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reglist.read_and_verbose_print()
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if reglist.is_all_field_value(1, self.memmap_registers[reg]):

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