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Fix up rtclock and smm_dma modules and cpu hal+unit tests
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1 parent 7d45974 commit 364ae34

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5 files changed

+64
-62
lines changed

5 files changed

+64
-62
lines changed

‎chipsec/hal/intel/cpu.py‎

Lines changed: 20 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ def get_number_physical_processor_per_package(self) -> int:
105105

106106
# determine number of logical processors in the core
107107
def get_number_threads_from_APIC_table(self) -> int:
108-
_acpi = acpi.ACPI(self.cs)
108+
_acpi = self.cs.hals.ACPI
109109
dACPIID = {}
110110
for apic in _acpi.get_parse_ACPI_table(acpi.ACPI_TABLE_SIG_APIC): # (table_header, APIC_object, table_header_blob, table_blob)
111111
_, APIC_object, _, _ = apic
@@ -154,12 +154,9 @@ def get_number_sockets_from_APIC_table(self) -> int:
154154
# Return SMRR MSR physical base and mask
155155
#
156156
def get_SMRR(self) -> Tuple[int, int]:
157-
if self.cs.is_intel():
158-
smrambase = self.cs.register.read_field('IA32_SMRR_PHYSBASE', 'PhysBase', True)
159-
smrrmask = self.cs.register.read_field('IA32_SMRR_PHYSMASK', 'PhysMask', True)
160-
elif self.cs.is_amd():
161-
smrambase = self.cs.register.read_field('SMM_BASE', 'SMMBASE', True)
162-
smrrmask = self.cs.register.read_field('SMMMASK', 'TSEGMASK', True)
157+
smrambase = self.cs.register.get_list_by_name('8086.MSR.IA32_SMRR_PHYSBASE').read_field('PhysBase')[0]
158+
smrrmask = self.cs.register.get_list_by_name('8086.MSR.IA32_SMRR_PHYSMASK').read_field('PhysMask')[0]
159+
163160
return (smrambase, smrrmask)
164161

165162
#
@@ -176,24 +173,19 @@ def get_SMRR_SMRAM(self) -> Tuple[int, int, int]:
176173
# Returns TSEG base, limit and size
177174
#
178175
def get_TSEG(self) -> Tuple[int, int, int]:
179-
if self.cs.is_intel():
180-
if self.cs.is_server():
181-
# tseg register has base and limit
182-
tseg_base = self.cs.register.read_field('TSEG_BASE', 'base', preserve_field_position=True)
183-
tseg_limit = self.cs.register.read_field('TSEG_LIMIT', 'limit', preserve_field_position=True)
184-
tseg_limit += 0xFFFFF
185-
else:
186-
# TSEG base is in TSEGMB, TSEG limit is BGSM - 1
187-
tseg_base = self.cs.register.read_field('PCI0.0.0_TSEGMB', 'TSEGMB', preserve_field_position=True)
188-
bgsm = self.cs.register.read_field('PCI0.0.0_BGSM', 'BGSM', preserve_field_position=True)
189-
tseg_limit = bgsm - 1
176+
if self.cs.is_server():
177+
# tseg register has base and limit
178+
tseg_base = self.cs.register.get_list_by_name('8086.MEMMAP_VTD.TSEG_BASE').read_field('base', True)[0]
179+
tseg_limit = self.cs.register.get_list_by_name('8086.MEMMAP_VTD.TSEG_LIMIT').read_field('limit', True)[0]
180+
tseg_limit += 0xFFFFF
181+
else:
182+
# TSEG base is in TSEGMB, TSEG limit is BGSM - 1
183+
tseg_base = self.cs.register.get_list_by_name('8086.HOSTCTL.TSEGMB').read_field('TSEGMB', True)[0]
184+
bgsm = self.cs.register.get_list_by_name('8086.HOSTCTL.BGSM').read_field('BGSM', True)[0]
185+
tseg_limit = bgsm - 1
186+
187+
tseg_size = tseg_limit - tseg_base + 1
190188

191-
tseg_size = tseg_limit - tseg_base + 1
192-
elif self.cs.is_amd():
193-
tseg_base = self.cs.register.read_field('SMMADDR', 'TSEGBASE', preserve_field_position=True)
194-
tseg_mask = self.cs.register.read_field('SMMMASK', 'TSEGMASK', preserve_field_position=True)
195-
tseg_size = ((~tseg_mask + 0xFFFFFFFFFFFF) + 1)
196-
tseg_limit = tseg_base + tseg_size
197189
return (tseg_base, tseg_limit, tseg_size)
198190

199191
#
@@ -222,19 +214,10 @@ def get_SMRAM(self) -> Tuple[int, int, int]:
222214
# Check that SMRR is supported by CPU in IA32_MTRRCAP_MSR[SMRR]
223215
#
224216
def check_SMRR_supported(self) -> bool:
225-
if self.cs.is_intel():
226-
mtrrcap_msr_reg = self.cs.register.read('MTRRCAP')
227-
if logger().HAL:
228-
self.cs.register.print('MTRRCAP', mtrrcap_msr_reg)
229-
smrr = self.cs.register.get_field('MTRRCAP', mtrrcap_msr_reg, 'SMRR')
230-
return (1 == smrr)
231-
elif self.cs.is_amd():
232-
smmmask_msr_reg = self.cs.register.read('SMMMASK')
233-
if logger().HAL:
234-
self.cs.register.print('SMMMASK', smmmask_msr_reg)
235-
avalid = self.cs.register.get_field('SMMMASK', smmmask_msr_reg, 'AVALID')
236-
tvalid = self.cs.register.get_field('SMMMASK', smmmask_msr_reg, 'TVALID')
237-
return (1 == avalid and 1 == tvalid)
217+
mtrrcap_msr_reg = self.cs.register.get_list_by_name('8086.MSR.MTRRCAP')
218+
mtrrcap_msr_reg.read_and_hal_print()
219+
return mtrrcap_msr_reg.is_any_field_value(1, 'SMRR')
220+
238221
#
239222
# Dump CPU page tables at specified physical base of paging-directory hierarchy (CR3)
240223
#

‎chipsec/library/register.py‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -334,10 +334,21 @@ def read_and_verbose_print(self):
334334
if logger().VERBOSE:
335335
self.print()
336336

337-
def read_field(self, field: str) -> List[int]:
337+
def read_and_hal_print(self):
338+
self.read()
339+
if logger().HAL:
340+
self.print()
341+
342+
def read_field(self, field: str, preserve_field_position: Optional[bool] = False) -> List[int]:
343+
ret = []
344+
for inst in self:
345+
ret.append(inst.read_field(field, preserve_field_position))
346+
return ret
347+
348+
def get_field(self, field: str, preserve_field_position: Optional[bool] = False) -> List[int]:
338349
ret = []
339350
for inst in self:
340-
ret.append(inst.read_field(field))
351+
ret.append(inst.get_field(field, preserve_field_position))
341352
return ret
342353

343354
def write(self, value: int) -> None:

‎chipsec/modules/common/rtclock.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
from chipsec.module_common import BaseModule, MTAG_BIOS, MTAG_HWCONFIG
4343
from chipsec.library.returncode import ModuleResult
4444
from chipsec.hal.common.cmos import CMOS
45-
from chipsec.config import CHIPSET_CODE_AVN
45+
# from chipsec.config import CHIPSET_CODE_AVN
4646
from typing import List
4747
TAGS = [MTAG_BIOS, MTAG_HWCONFIG]
4848

@@ -60,7 +60,7 @@ def __init__(self):
6060
})
6161

6262
def is_supported(self) -> bool:
63-
if self.cs.is_core() or (self.cs.Cfg.get_chipset_code() == CHIPSET_CODE_AVN):
63+
if self.cs.is_core(): #or (self.cs.Cfg.get_chipset_code() == CHIPSET_CODE_AVN):
6464
if self.cs.register.is_defined('RC'):
6565
return True
6666
self.logger.log_important('RC register not defined for platform. Skipping module.')

‎chipsec/modules/common/smm_dma.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ class smm_dma(BaseModule):
6969
def __init__(self):
7070
BaseModule.__init__(self)
7171
self.cs.set_scope({
72-
"MSR_BIOS_DONE": "8086.MSR.MSR_BIOS_DONE",
72+
"MSR_BIOS_DONE": "8086.MSR",
7373
})
7474

7575
def is_supported(self) -> bool:

‎tests/hal/test_cpu.py‎

Lines changed: 28 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -210,17 +210,20 @@ def test_hal_cpu_get_number_sockets_from_APIC_table(self):
210210

211211
def test_hal_cpu_get_SMRR(self):
212212
mock_self = Mock()
213-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0xFFC00000]
213+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0xFFC00000]]
214214
result = CPU.get_SMRR(mock_self)
215215
self.assertEqual(result, (0x88400000, 0xFFC00000))
216216

217217
def test_hal_cpu_get_SMRR_cmd(self):
218218
mock_self = Mock()
219-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0xFFC00000]
220-
call_1 = call('IA32_SMRR_PHYSBASE', 'PhysBase', True)
221-
call_2 = call('IA32_SMRR_PHYSMASK', 'PhysMask', True)
219+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0xFFC00000]]
220+
reg_call_1 = call('8086.MSR.IA32_SMRR_PHYSBASE')
221+
reg_call_2 = call('8086.MSR.IA32_SMRR_PHYSMASK')
222+
field_call_1 = call('PhysBase') # TODO: Do these two \/ need to have a `, True` added to it?
223+
field_call_2 = call('PhysMask')
222224
CPU.get_SMRR(mock_self)
223-
mock_self.cs.register.read_field.assert_has_calls([call_1, call_2])
225+
self.assertEqual(mock_self.cs.register.get_list_by_name.call_args_list, [call(), reg_call_1, reg_call_2])
226+
self.assertEqual(mock_self.cs.register.get_list_by_name().read_field.call_args_list, [field_call_1, field_call_2])
224227

225228
def test_hal_cpu_get_SMRR_SMRAM(self):
226229
mock_self = Mock()
@@ -231,37 +234,43 @@ def test_hal_cpu_get_SMRR_SMRAM(self):
231234

232235
def test_hal_cpu_get_TSEG_is_server_true_cmd(self):
233236
mock_self = Mock()
234-
call_1 = call('TSEG_BASE', 'base', preserve_field_position=True)
235-
call_2 = call('TSEG_LIMIT', 'limit', preserve_field_position=True)
237+
reg_call_1 = call('8086.MEMMAP_VTD.TSEG_BASE')
238+
reg_call_2 = call('8086.MEMMAP_VTD.TSEG_LIMIT')
239+
field_call_1 = call('base', True)
240+
field_call_2 = call('limit', True)
241+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0x88700000]]
236242
mock_self.cs.is_server.return_value = True
237-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0x88700000]
238243
CPU.get_TSEG(mock_self)
239-
mock_self.cs.register.read_field.assert_has_calls([call_1, call_2])
244+
self.assertEqual(mock_self.cs.register.get_list_by_name.call_args_list, [call(), reg_call_1, reg_call_2])
245+
self.assertEqual(mock_self.cs.register.get_list_by_name().read_field.call_args_list, [field_call_1, field_call_2])
240246

241247
def test_hal_cpu_get_TSEG_is_server_true(self):
242248
mock_self = Mock()
243249
mock_self.cs.is_server.return_value = True
244-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0x88700000]
250+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0x88700000]]
245251
expected_result = (0x88400000, 0x887FFFFF, 0x400000)
246252
result = CPU.get_TSEG(mock_self)
247253
self.assertEqual(result, expected_result)
248254

249255
def test_hal_cpu_get_TSEG_is_server_false(self):
250256
mock_self = Mock()
251257
mock_self.cs.is_server.return_value = False
252-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0x88800000]
258+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0x88800000]]
253259
expected_result = (0x88400000, 0x887FFFFF, 0x400000)
254260
result = CPU.get_TSEG(mock_self)
255261
self.assertEqual(result, expected_result)
256262

257263
def test_hal_cpu_get_TSEG_is_server_false_cmd(self):
258264
mock_self = Mock()
259-
call_1 = call('PCI0.0.0_TSEGMB', 'TSEGMB', preserve_field_position=True)
260-
call_2 = call('PCI0.0.0_BGSM', 'BGSM', preserve_field_position=True)
265+
reg_call_1 = call('8086.HOSTCTL.TSEGMB')
266+
reg_call_2 = call('8086.HOSTCTL.BGSM')
267+
field_call_1 = call('TSEGMB', True)
268+
field_call_2 = call('BGSM', True)
269+
mock_self.cs.register.get_list_by_name().read_field.side_effect = [[0x88400000], [0x88800000]]
261270
mock_self.cs.is_server.return_value = False
262-
mock_self.cs.register.read_field.side_effect = [0x88400000, 0x88800000]
263271
CPU.get_TSEG(mock_self)
264-
mock_self.cs.register.read_field.assert_has_calls([call_1, call_2])
272+
self.assertEqual(mock_self.cs.register.get_list_by_name.call_args_list, [call(), reg_call_1, reg_call_2])
273+
self.assertEqual(mock_self.cs.register.get_list_by_name().read_field.call_args_list, [field_call_1, field_call_2])
265274

266275
def test_hal_cpu_get_SMRAM_smrr_true(self):
267276
mock_self = MagicMock()
@@ -281,21 +290,20 @@ def test_hal_cpu_get_SMRAM_smrr_false(self):
281290

282291
def test_hal_cpu_check_SMRR_supported_cmd2(self):
283292
mock_self = Mock()
284-
mock_self.cs.register.read.return_value = 0x88442200
285-
mock_self.cs.register.get_field.return_value = 0
293+
mock_self.cs.register.get_list_by_name().is_any_field_value.return_value = 0
286294
CPU.check_SMRR_supported(mock_self)
287-
mock_self.cs.register.read.assert_called_with('MTRRCAP')
295+
mock_self.cs.register.get_list_by_name.assert_called_with('8086.MSR.MTRRCAP')
288296

289297
def test_hal_cpu_check_SMRR_supported_cmd(self):
290298
mock_self = Mock()
291299
mock_self.cs.register.read.return_value = 0x88442200
292300
mock_self.cs.register.get_field.return_value = 0
293301
CPU.check_SMRR_supported(mock_self)
294-
mock_self.cs.register.get_field.assert_called_with('MTRRCAP', 0x88442200, 'SMRR')
302+
mock_self.cs.register.get_list_by_name().is_any_field_value.assert_called_with(1, 'SMRR')
295303

296304
def test_hal_cpu_check_SMRR_supported_false(self):
297305
mock_self = Mock()
298-
mock_self.cs.register.get_field.return_value = 0
306+
mock_self.cs.register.get_list_by_name().is_any_field_value.return_value = 0
299307
result = CPU.check_SMRR_supported(mock_self)
300308
self.assertFalse(result)
301309

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