Minor bug fixes

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>

Author: BrentHoltsclaw

chipsec/hal/common/mmio.py

@@ -252,10 +252,10 @@ def get_MMIO_BAR_base_address(self, bar_name: str, instance: Optional['PCIObj']
                 mmioaddr <<= bar.mmio_align
             base += mmioaddr
 
-        if bar.limit_register and bar.limit_field and bar.limit_align:
+        if bar.limit_register and bar.limit_field and bar.limit_align and instance is not None:
             limit_field = bar.limit_field
             limit_bar = bar.limit_register
-            lim_reg = self.cs.Cfg.get_register_obj(limit_bar, instance)
+            lim_reg = self.cs.register.get_instance_by_name(limit_bar, instance)
             limit = lim_reg.read_field(limit_field)
             if bar.limit_align:
                 limit_align = bar.limit_align
@@ -276,7 +276,7 @@ def get_MMIO_BAR_base_address(self, bar_name: str, instance: Optional['PCIObj']
         if size == 0:
             size = DEFAULT_MMIO_BAR_SIZE
         self.logger.log_hal('[mmio] {}: 0x{:016X} (size = 0x{:X})'.format(bar_name, base, size))
-        if base == 0:
+        if base == 0 and bar.fixed_address is None:
             self.logger.log_hal('[mmio] Base address was determined to be 0.')
             raise CSReadError('[mmio] Base address was determined to be 0')
 
@@ -387,7 +387,7 @@ def is_MMIO_BAR_valid(self, bar_name, instance=None):
         if bar.register:
             if bar.valid:
                 bar_en_field = bar.valid
-                bar_reg = self.cs.Cfg.register.get_list_by_name(bar.register).filter_by_instance(instance)
+                bar_reg = self.cs.register.get_list_by_name(bar.register).filter_by_instance(instance)
                 is_valid = bar_reg.is_all_field_value(1, bar_en_field)
         return is_valid
 

chipsec/hal/intel/spi.py

@@ -169,7 +169,7 @@ def set_instance(self, instance: 'PCIObj') -> None:
     def get_SPI_MMIO_base(self) -> int:
         spi_base = 0
         if self.mmio.is_MMIO_BAR_defined('8086.SPI.SPIBAR'):
-            (spi_base, _) = self.mmio.get_MMIO_BAR_base_address('8086.SPI.SPIBAR')
+            (spi_base, _) = self.mmio.get_MMIO_BAR_base_address('8086.SPI.SPIBAR', self.instance)
         else:
             self.logger.log_hal('[spi] get_SPI_MMIO_base(): SPIBAR not defined. Returning spi_base = 0.')
         self.logger.log_hal(f'[spi] SPI MMIO base: 0x{spi_base:016X} (assuming below 4GB)')
@@ -717,6 +717,7 @@ def get_SPI_SFDP(self) -> bool:
     #
 
     def get_SPI_JEDEC_ID(self) -> int:
+
         if self.hsfs.has_field('FCYCLE'):
             self.check_hardware_sequencing()
 

chipsec/library/acpi_tables.py

@@ -1738,7 +1738,7 @@ def parseGHESS(self, table_content: bytes, _type: int) -> int:
             title = 'Generic Hardware Error Source Version 2'
             readAckReg_str = self.parseAddress(table_content[64:76])
             readAckPresv = struct.unpack('<Q', table_content[76:84])[0]
-            readAckWr = struct.unpack('<Q', table_content[84:88])[0]
+            readAckWr = struct.unpack('<Q', table_content[84:92])[0]
             extra_str = f'''
     Read Ack Register - {readAckReg_str}
     Read Ack Preserve                             : 0x{readAckPresv:016X}