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npmitchenpmitche
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Update rtclock module
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1 parent 4877f96 commit 43d3c36

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3 files changed

+28
-23
lines changed

3 files changed

+28
-23
lines changed

‎chipsec/cfg/parsers/registers/mm_msgbus.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,10 +59,10 @@ def read(self):
5959
"""Read the object"""
6060
self.logger.log_debug(f'reading {self.name}')
6161
_cs = cs()
62-
self.value = _cs.mm_msgbus.reg_read(self.port, self.offset)
62+
self.value = _cs.hals.MsgBus.mm_msgbus_reg_read(self.port, self.offset)
6363
return self.value
6464

6565
def write(self, value):
6666
"""Write the object"""
6767
_cs = cs()
68-
_cs.mm_msgbus.reg_write(self.port, self.offset, value)
68+
_cs.MsgBus.mm_msgbus_reg_write(self.port, self.offset, value)

‎chipsec/hal/common/cmos.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -52,35 +52,35 @@ def __init__(self, cs):
5252
super(CMOS, self).__init__(cs)
5353

5454
def read_cmos_high(self, offset: int) -> int:
55-
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset)
56-
return self.cs.hals.Io.read(CMOS_DATA_PORT_HIGH)
55+
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset, 1)
56+
return self.cs.hals.Io.read(CMOS_DATA_PORT_HIGH, 1)
5757

5858
def write_cmos_high(self, offset: int, value: int) -> None:
59-
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset)
60-
self.cs.hals.Io.write(CMOS_DATA_PORT_HIGH, value)
59+
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, offset, 1)
60+
self.cs.hals.Io.write(CMOS_DATA_PORT_HIGH, value, 1)
6161

6262
def read_cmos_low(self, offset: int) -> int:
63-
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, 0x80 | offset)
64-
return self.cs.hals.Io.read(CMOS_DATA_PORT_LOW)
63+
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, 0x80 | offset, 1)
64+
return self.cs.hals.Io.read(CMOS_DATA_PORT_LOW, 1)
6565

6666
def write_cmos_low(self, offset: int, value: int) -> None:
67-
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, offset)
68-
self.cs.hals.Io.write(CMOS_DATA_PORT_LOW, value)
67+
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, offset, 1)
68+
self.cs.hals.Io.write(CMOS_DATA_PORT_LOW, value, 1)
6969

7070
def dump_low(self) -> List[int]:
7171
cmos_buf = [0xFF] * 0x80
72-
orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_LOW)
72+
orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_LOW, 1)
7373
for off in range(0x80):
7474
cmos_buf[off] = self.read_cmos_low(off)
75-
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, orig)
75+
self.cs.hals.Io.write(CMOS_ADDR_PORT_LOW, orig, 1)
7676
return cmos_buf
7777

7878
def dump_high(self) -> List[int]:
7979
cmos_buf = [0xFF] * 0x80
80-
orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_HIGH)
80+
orig = self.cs.hals.Io.read(CMOS_ADDR_PORT_HIGH, 1)
8181
for off in range(0x80):
8282
cmos_buf[off] = self.read_cmos_high(off)
83-
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, orig)
83+
self.cs.hals.Io.write(CMOS_ADDR_PORT_HIGH, orig, 1)
8484
return cmos_buf
8585

8686
def dump(self) -> None:

‎chipsec/modules/common/rtclock.py‎

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
- This module will only run on Core platforms
4040
"""
4141

42+
from chipsec.library.exceptions import CSReadError
4243
from chipsec.module_common import BaseModule, MTAG_BIOS, MTAG_HWCONFIG
4344
from chipsec.library.returncode import ModuleResult
4445
from chipsec.hal.common.cmos import CMOS
@@ -69,31 +70,35 @@ def is_supported(self) -> bool:
6970
return False
7071

7172
def check_rtclock(self) -> int:
72-
ll = ul = 0
73+
ll = ul = False
7374
rc_list = self.cs.register.get_list_by_name('RC')
7475
res = ModuleResult.FAILED
7576
for rc in rc_list:
76-
check_config_regs = rc.read() != 0xFFFFFFFF
77+
try:
78+
check_config_regs = rc.read() != 0xFFFFFFFF
79+
except CSReadError as err:
80+
check_config_regs = False
81+
self.logger.log_debug(f'Error reading RC register: {err}')
7782

7883
if check_config_regs:
7984
rc.print()
80-
ll = rc.get_field('LL')
81-
ul = rc.get_field('UL')
85+
ll = rc.is_all_field_value(1, 'LL')
86+
ul = rc.is_all_field_value(1, 'UL')
8287
elif self.user_request:
8388
self.logger.log_important('Writing to CMOS to determine write protection (original values will be restored)')
8489

8590
original_val = self.cmos.read_cmos_low(self.test_offset)
8691
self.cmos.write_cmos_low(self.test_offset, original_val ^ self.test_value)
8792
if original_val == self.cmos.read_cmos_low(self.test_offset):
88-
ll = 1
93+
ll = True
8994
else:
9095
self.logger.log_important('Restoring original value')
9196
self.cmos.write_cmos_low(self.test_offset, original_val)
9297

9398
original_val = self.cmos.read_cmos_high(self.test_offset)
9499
self.cmos.write_cmos_high(self.test_offset, original_val ^ self.test_value)
95100
if original_val == self.cmos.read_cmos_high(self.test_offset):
96-
ul = 1
101+
ul = True
97102
else:
98103
self.logger.log_important('Restoring original value')
99104
self.cmos.write_cmos_high(self.test_offset, original_val)
@@ -104,16 +109,16 @@ def check_rtclock(self) -> int:
104109
self.result.setStatusBit(self.result.status.VERIFY)
105110
return self.result.getReturnCode(ModuleResult.WARNING)
106111

107-
if ll == 1:
112+
if ll:
108113
self.logger.log_good('Protected bytes (0x38-0x3F) in low 128-byte bank of RTC memory are locked')
109114
else:
110115
self.logger.log_bad('Protected bytes (0x38-0x3F) in low 128-byte bank of RTC memory are not locked')
111-
if ul == 1:
116+
if ul:
112117
self.logger.log_good('Protected bytes (0x38-0x3F) in high 128-byte bank of RTC memory are locked')
113118
else:
114119
self.logger.log_bad('Protected bytes (0x38-0x3F) in high 128-byte bank of RTC memory are not locked')
115120

116-
if (ll == 1) and (ul == 1):
121+
if ll and ul:
117122
res = ModuleResult.PASSED
118123
self.logger.log_passed('Protected locations in RTC memory are locked')
119124
else:

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