Fix some unit tests from running in Windows

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>

Author: npmitche

chipsec/cfg/8086/kbl.xml

@@ -42,7 +42,7 @@ chipsec@intel.com
   </msr>
 
   <memory>
-    <range name="TPM" access="mmio" address="0xFED40000" size="0x10000" config="TPM.tpm12.xml" />
+    <range name="TPM" access="mmio" address="0xFED40000" limit="0xFED4FFFF" config="TPM.tpm12.xml" />
   </memory>
 
 </configuration>

chipsec/cfg/8086/mtl.xml

@@ -57,7 +57,7 @@ chipsec@intel.com
   <!--                                      -->
   <!-- #################################### -->
   <memory>
-    <range name="TPM" access="mmio" address="0xFED40000" size="0x10000" config="TPM.tpm12.xml" />
+    <range name="TPM" access="mmio" address="0xFED40000" limit="0xFED4FFFF" config="TPM.tpm12.xml" />
   </memory>
 
 </configuration>

chipsec/hal/common/io.py

@@ -85,7 +85,7 @@ def dump_range(self, range_base: int, range_size: int, size: int = 1) -> None:
         logger().log(f"[io] I/O register range [0x{range_base:04X}:0x{range_base:04X}+{range_size:04X}]:")
         read_ranges = self.read_range(range_base, range_size, size)
         for i, read_val in enumerate(read_ranges):
-            logger().log(f'+{size * i:04X}: {read_val:{f'0{size * 2:d}X'}}')
+            logger().log(f'+{size * i:04X}: {read_val:{f"0{size * 2:d}X"}}')
 
     def read_port_byte(self, io_port: int) -> int:
         return self.read(io_port, 1)

chipsec/hal/common/msr.py

@@ -68,7 +68,7 @@ def __init__(self, cs):
     def get_cpu_thread_count(self) -> int:
         if not self.topo:
             self.topo = self.cs.hals.CPU.get_cpu_topology()
-        self.logger.log_hal(f'[Msr] # of logical CPUs: {self.topo['threads']:d}')
+        self.logger.log_hal(f'[Msr] # of logical CPUs: {self.topo["threads"]:d}')
         return self.topo['threads']
 
 

chipsec/hal/hals.py

@@ -105,7 +105,7 @@ def update_available_hals(self) -> Dict[str, Any]:
         for hal_dir in hal_dirs:
             hals += ([f'{hal_dir}.{i[:-3]}' for i in os.listdir(os.path.join(hal_base_dir, hal_dir)) if i[-3:] == ".py" and not i[:2] == "__"])
         logger().log_debug('[CHIPSEC] Loaded HALs:')
-        logger().log_debug(f'   {"\n".join(hals)}')
+        logger().log_debug(f'   {os.linesep.join(hals)}')
         module = None
         halsdata = []
         for hal in hals:

tests/modules/tgl/enumeration.json

@@ -82,18 +82,23 @@
   },
   "read_pci_reg": {
     "(0,0,0,0,4)": [
+      "1493467270",
       "1493467270"
     ],
     "(0,0,0,8,1)": [
+      "1",
       "1"
     ],
     "(0,0,1,0,4)": [
+      "67174402",
       "67174402"
     ],
     "(0,0,1,8,1)": [
+      "0",
       "0"
     ],
     "(0,0,2,0,4)": [
+      "4294967295",
       "4294967295"
     ],
     "(0,0,3,0,4)": [