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Commit 7208aa4

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Fix modules debugenabled and me_mfg_mode
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1 parent 7162f26 commit 7208aa4

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2 files changed

+44
-34
lines changed

2 files changed

+44
-34
lines changed

chipsec/modules/common/debugenabled.py

Lines changed: 40 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,10 @@ class debugenabled(BaseModule):
5252

5353
def __init__(self):
5454
BaseModule.__init__(self)
55+
self.cs.set_scope({
56+
"ECTRL": "8086.DCI.ECTRL",
57+
"IA32_DEBUG_INTERFACE": "8086.MSR.IA32_DEBUG_INTERFACE"
58+
})
5559
self.is_enable_set = False
5660
self.is_debug_set = False
5761
self.is_lock_set = True
@@ -69,11 +73,15 @@ def check_dci(self) -> int:
6973
TestFail = ModuleResult.PASSED
7074
self.logger.log('')
7175
self.logger.log('[*] Checking DCI register status')
72-
ectrl = self.cs.register.read('ECTRL')
73-
HDCIEN = self.cs.register.get_field('ECTRL', ectrl, 'ENABLE') == 1
74-
if self.logger.VERBOSE:
75-
self.cs.register.print('ECTRL', ectrl)
76-
if HDCIEN:
76+
ectrl = self.cs.register.get_list_by_name('ECTRL')
77+
# ectrl = self.cs.register.read('ECTRL')
78+
ectrl.read_and_verbose_print()
79+
hdcien_mask = ectrl[0].get_field_mask('ENABLE', True)
80+
81+
# HDCIEN = self.cs.register.get_field('ECTRL', ectrl, 'ENABLE') == 1
82+
if ectrl.is_all_field_value(ectrl[0].get_field('ENABLE'), 'ENABLE'):
83+
self.logger.log_good('CPU debug enable is set consistently')
84+
if ectrl.is_any_value(hdcien_mask, 'ENABLE'):
7785
self.logger.log_bad('DCI Debug is enabled')
7886
TestFail = ModuleResult.FAILED
7987
self.result.setStatusBit(self.result.status.DEBUG_FEATURE)
@@ -85,33 +93,34 @@ def check_cpu_debug_enable(self) -> int:
8593
self.logger.log('')
8694
self.logger.log('[*] Checking IA32_DEBUG_INTERFACE MSR status')
8795
TestFail = ModuleResult.PASSED
88-
for tid in range(self.cs.hals.Msr.get_cpu_thread_count()):
89-
dbgiface = self.cs.register.read('IA32_DEBUG_INTERFACE', tid)
90-
IA32_DEBUG_INTERFACE_DEBUGENABLE = self.cs.register.get_field('IA32_DEBUG_INTERFACE', dbgiface, 'ENABLE') == 1
91-
IA32_DEBUG_INTERFACE_DEBUGELOCK = self.cs.register.get_field('IA32_DEBUG_INTERFACE', dbgiface, 'LOCK') == 1
92-
IA32_DEBUG_INTERFACE_DEBUGEOCCURED = self.cs.register.get_field('IA32_DEBUG_INTERFACE', dbgiface, 'DEBUG_OCCURRED') == 1
93-
94-
if self.logger.VERBOSE:
95-
self.cs.register.print('IA32_DEBUG_INTERFACE', dbgiface)
96-
97-
if IA32_DEBUG_INTERFACE_DEBUGENABLE:
98-
self.logger.log_bad('CPU debug enable requested by software.')
99-
self.is_enable_set = True
100-
TestFail = ModuleResult.FAILED
101-
self.result.setStatusBit(self.result.status.DEBUG_FEATURE)
102-
if not IA32_DEBUG_INTERFACE_DEBUGELOCK:
103-
self.logger.log_bad('CPU debug interface is not locked.')
104-
self.is_lock_set = False
105-
TestFail = ModuleResult.FAILED
106-
self.result.setStatusBit(self.result.status.LOCKS)
107-
if IA32_DEBUG_INTERFACE_DEBUGEOCCURED:
108-
self.logger.log_important('Debug Occurred bit set in IA32_DEBUG_INTERFACE MSR')
109-
self.is_debug_set = True
110-
self.result.setStatusBit(self.result.status.DEBUG_FEATURE)
111-
if TestFail == ModuleResult.PASSED:
112-
TestFail = ModuleResult.WARNING
96+
dbg_regs = self.cs.register.get_list_by_name('IA32_DEBUG_INTERFACE')
97+
dbg_regs.read_and_verbose_print()
98+
enable_mask = dbg_regs[0].get_field_mask('ENABLE', True)
99+
occured_mask = dbg_regs[0].get_field_mask('DEBUG_OCCURRED', True)
100+
101+
102+
if dbg_regs.is_all_field_value(dbg_regs[0].get_field('ENABLE'), 'ENABLE'):
103+
self.logger.log_good('CPU debug enable is set consitently')
104+
if dbg_regs.is_any_field_value(enable_mask, 'ENABLE'):
105+
self.logger.log_bad('CPU debug enable requested by software.')
106+
self.is_enable_set = True
107+
TestFail = ModuleResult.FAILED
108+
self.result.setStatusBit(self.result.status.DEBUG_FEATURE)
109+
if dbg_regs.is_all_field_value(dbg_regs[0].get_field('LOCK'), 'LOCK'):
110+
self.logger.log_good('CPU debug lock is set consitently')
111+
if dbg_regs.is_any_field_value(0, 'LOCK'):
112+
self.logger.log_bad('CPU debug interface is not locked.')
113+
self.is_lock_set = False
114+
TestFail = ModuleResult.FAILED
115+
self.result.setStatusBit(self.result.status.LOCKS)
116+
if dbg_regs.is_any_field_value(occured_mask, 'DEBUG_OCCURRED'):
117+
self.logger.log_important('Debug Occurred bit set in IA32_DEBUG_INTERFACE MSR')
118+
self.is_debug_set = True
119+
self.result.setStatusBit(self.result.status.DEBUG_FEATURE)
113120
if TestFail == ModuleResult.PASSED:
114-
self.logger.log_good('CPU debug interface state is correct.')
121+
TestFail = ModuleResult.WARNING
122+
if TestFail == ModuleResult.PASSED:
123+
self.logger.log_good('CPU debug interface state is correct.')
115124
return TestFail
116125

117126
def run(self, module_argv: List[str]) -> int:

chipsec/modules/common/me_mfg_mode.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -102,12 +102,13 @@ class me_mfg_mode(BaseModule):
102102
def __init__(self):
103103
BaseModule.__init__(self)
104104
self.cs.set_scope({
105-
"MEI1": "8086.MEI1",
106-
"HFS": "8086.MEI1.HFS",
105+
"MEI1": "8086", # TODO: Must not have .MEI1 at the end. The ending item must only be in the key.
106+
"HFS": "8086.MEI1",
107107
})
108108

109109
def is_supported(self) -> bool:
110-
if self.cs.device.get_bus('MEI1') and self.cs.device.is_enabled('MEI1'):
110+
self.mei1_dev = self.cs.device.get_obj('MEI1')
111+
if self.mei1_dev.instances and self.mei1_dev.instances[0].bus is not None:
111112
return True
112113
else:
113114
self.logger.log_important('MEI1 not enabled. Skipping module.')

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