Update configs and files for some external tests

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>

Author: npmitche

chipsec/cfg/8086/HOSTCTL/hostctl11gen.xml

@@ -1,16 +1,6 @@
 <?xml version="1.0"?>
 <configuration>
 
-  <mmio>
-    <bar name="PXPEPBAR" register="PXPEPBAR" base_field="PXPEPBAR" size="0x1000" enable_bit="0" desc="PCI Express Egress Port Register Range"/>
-    <bar name="MCHBAR"   register="MCHBAR" base_field="MCHBAR" size="0x8000" enable_bit="0" desc="Host Memory Mapped Register Range"/>
-    <bar name="MMCFG"    register="PCIEXBAR" base_field="PXPEPBAR" size="0x1000" enable_bit="0" desc="PCI Express Register Range"/>
-    <bar name="DMIBAR"   register="DMIBAR" base_field="DMIBAR" size="0x1000" enable_bit="0" desc="Root Complex Register Range"/>
-    <!-- VT-d BARs -->
-    <bar name="VTBAR"    register="VTBAR"    base_field="Base" size="0x1000" enable_field="Enable" desc="Intel VT-d Register Register Range"/>
-    <bar name="GFXVTBAR" register="GFXVTBAR" base_field="Base" size="0x1000" enable_field="Enable" desc="Intel Processor Graphics VT-d Register Range"/>
-  </mmio>
-
   <!-- #################################### -->
   <!--                                      -->
   <!-- Configuration registers              -->

chipsec/cfg/8086/MMIO/pwrm0.xml

@@ -11,6 +11,10 @@
             <field name="SCIS"    bit="0" size="3" desc="SCI IRQ Select"/>
         </register>
         <register name="PM_CFG" type="mmio" bar="PWRMBASE" offset="0x1818" size="4" desc="Power Management Configuration Reg 1"/>
+        <register name="ETR3" type="mmio" bar="PWRMBASE" offset="0x1048" size="4" desc="Extended Test Mode Register 3">
+            <field name="CF9GR" bit="20" size="1" desc="CF9h Global Reset"/>
+            <field name="CF9LOCK" bit="31" size="1" desc="CF9h Lock"/>
+        </register>
     </registers>
 
     <controls>

chipsec/cfg/8086/MSR/msr2.xml

@@ -134,6 +134,19 @@
       <field name="EB_LEG_BITMAP_BASE" bit="12" size="52" desc="Linear address bits of legacy code page bitmap" />
   </register>
 
+    <register name="MSR_PKG_CST_CONFIG_CONTROL" type="msr" scope="core" msr="0xE2" desc="C-State Configuration Register">
+      <field name="LOCK" bit="15" size="1" desc="Lock MSR_PKG_CST_CONFIG_CONTROL register" />
+      <field name="Reserved2" bit="11" size="4" desc="Reserved" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
+      <field name="IO_MWIAT_REDIRECTION" bit="10" size="1" desc="map IO_read to PMG_IO_BASE_ADDRBASE + offset to MWAIT" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
+      <field name="Reserved" bit="4" size="6" desc="Reserved" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
+      <field name="MAX_PKG_C_STATE" bit="0" size="4" desc="Lowest C-state for the package" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
+    </register>
+
+    <register name="FEATURE_CONFIG" type="msr" msr="0x13C" scope="core" desc="FEATURE_CONFIG Register">
+      <field name="AES_DISABLE" bit="1" size="1" desc="Disable AES on Core" lockedby="FEATURE_CONFIG.Lock"/>
+      <field name="Lock" bit="0" size="1" desc="FEATURE_CONFIG Register Lock" />
+    </register>
+
   </registers>
 
   <controls>

chipsec/library/register.py

@@ -336,12 +336,11 @@ def has_field(self, reg_name: str, field_name: str) -> bool:
             reg_defs = self.cs.Cfg.get_reglist(reg_name)
         except RegisterNotFoundError:
             return False
-        for reg_def in reg_defs:
-            try:
-                return field_name in reg_def.fields
-            except KeyError:
-                return False
-        return False
+        upper_field_name = field_name.upper()
+        try:
+            return bool(reg_defs) and all([upper_field_name in reg_def.fields for reg_def in reg_defs])
+        except KeyError:
+            return False
 
     def get_match(self, name: str) -> List[str]:
         """

tests/modules/tgl/enumeration.json

@@ -132,7 +132,7 @@
   },
   "read_pci_reg": {
     "(0,0,0,0,4)": [
-      "1493467270"
+      "2585034886"
     ],
     "(0,0,0,8,1)": [
       "1"