Update to hals

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>

Author: npmitche

chipsec/hal/common/cpuid.py

@@ -40,10 +40,7 @@ def __init__(self, cs):
         self.helper = cs.helper
 
     def cpuid(self, eax: int, ecx: int) -> Tuple[int, int, int, int]:
-        logger().log_hal(f'[cpuid] in: EAX=0x{eax:08X}, ECX=0x{ecx:08X}')
-        (eax, ebx, ecx, edx) = self.helper.cpuid(eax, ecx)
-        logger().log_hal(f'[cpuid] out: EAX=0x{eax:08X}, EBX=0x{ebx:08X}, ECX=0x{ecx:08X}, EDX=0x{edx:08X}')
-        return (eax, ebx, ecx, edx)
+        return self.cs.hals.CPU.cpuid(eax, ecx)
 
     def get_proc_info(self):
         (eax, _, _, _) = self.cpuid(0x01, 0x00)
@@ -53,7 +50,9 @@ def get_mfgid(self) -> str:
         (_,ebx, ecx, edx) = self.cpuid(0x00, 0x00)
         mfg_barray = ebx.to_bytes(4, byteorder) + edx.to_bytes(4, byteorder) + ecx.to_bytes(4, byteorder)
         return bytestostring(unpack('<12s', mfg_barray)[0])
+    
+
 
 
 
-haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': ['CpuId']} #change arch to CPUID genuine intel/amd
+haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': ['CpuId']}

chipsec/hal/common/ec.py

@@ -84,29 +84,29 @@ class EC(hal_base.HALBase):
     # Wait for EC input buffer empty
     def _wait_ec_inbuf_empty(self) -> bool:
         to = 1000
-        while (self.cs.hals.Io.read(IO_PORT_EC_STATUS) & EC_STS_IBF) and to:
+        while (self.cs.hals.Io.read(IO_PORT_EC_STATUS, 1) & EC_STS_IBF) and to:
             to = to - 1
         return True
 
     # Wait for EC output buffer full
     def _wait_ec_outbuf_full(self) -> bool:
         to = 1000
-        while not (self.cs.hals.Io.read(IO_PORT_EC_STATUS) & EC_STS_OBF) and to:
+        while not (self.cs.hals.Io.read(IO_PORT_EC_STATUS, 1) & EC_STS_OBF) and to:
             to = to - 1
         return True
 
     def write_command(self, command: int) -> None:
         self._wait_ec_inbuf_empty()
-        return self.cs.hals.Io.write(IO_PORT_EC_COMMAND, command)
+        return self.cs.hals.Io.write(IO_PORT_EC_COMMAND, command, 1)
 
     def write_data(self, data: int) -> None:
         self._wait_ec_inbuf_empty()
-        return self.cs.hals.Io.write(IO_PORT_EC_DATA, data)
+        return self.cs.hals.Io.write(IO_PORT_EC_DATA, data, 1)
 
     def read_data(self) -> Optional[int]:
         if not self._wait_ec_outbuf_full():
             return None
-        return self.cs.hals.Io.read(IO_PORT_EC_DATA)
+        return self.cs.hals.Io.read(IO_PORT_EC_DATA, 1)
 
     def read_memory(self, offset: int) -> Optional[int]:
         self.write_command(EC_COMMAND_ACPI_READ)
@@ -167,17 +167,17 @@ def write_range(self, start_offset: int, buffer: bytes) -> bool:
     # EC Intex I/O access
     #
     def read_idx(self, offset: int) -> int:
-        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF)
-        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF)
-        value = self.cs.hals.Io.read(IO_PORT_EC_INDEX_DATA)
+        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF, 1)
+        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF, 1)
+        value = self.cs.hals.Io.read(IO_PORT_EC_INDEX_DATA, 1)
         self.logger.log_hal(f'[ec] index read: offset 0x{offset:02X} > 0x{value:02X}:')
         return value
 
     def write_idx(self, offset: int, value: int) -> bool:
         self.logger.log_hal(f'[ec] index write: offset 0x{offset:02X} < 0x{value:02X}:')
-        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF)
-        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF)
-        self.cs.hals.Io.write(IO_PORT_EC_INDEX_DATA, value & 0xFF)
+        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF, 1)
+        self.cs.hals.Io.write(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF, 1)
+        self.cs.hals.Io.write(IO_PORT_EC_INDEX_DATA, value & 0xFF, 1)
         return True
 
 

chipsec/hal/common/interrupts.py

@@ -35,11 +35,11 @@
 from chipsec.hal import hal_base
 from chipsec.library.logger import logger, print_buffer_bytes
 from chipsec.hal.common.acpi import ACPI
+from chipsec.library.exceptions import CSReadError
 from chipsec.hal.common.acpi_tables import UEFI_TABLE, GAS
 from chipsec.library.defines import bytestostring
 
 SMI_APMC_PORT = 0xB2
-SMI_DATA_PORT = 0xB3
 
 NMI_TCO1_CTL = 0x8  # NMI_NOW is bit [8] in TCO1_CTL (or bit [1] in TCO1_CTL + 1)
 NMI_NOW = 0x1
@@ -76,14 +76,25 @@ def send_SW_SMI_timed(self, thread_id: int, SMI_code_port_value: int, SMI_data_p
 
     def send_SMI_APMC(self, SMI_code_port_value: int, SMI_data_port_value: int) -> None:
         logger().log_hal(f"[intr] sending SMI via APMC ports: code 0xB2 <- 0x{SMI_code_port_value:02X}, data 0xB3 <- 0x{SMI_data_port_value:02X}")
-        self.cs.hals.Io.write_port_byte(SMI_DATA_PORT, SMI_data_port_value)
-        return self.cs.hals.Io.write_port_byte(SMI_APMC_PORT, SMI_code_port_value)
+        SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
+        return self.cs.hals.Io.write_port_word(SMI_APMC_PORT, SMI_code_data)
 
     def send_NMI(self) -> None:
-        logger().log_hal("[intr] Sending NMI# through TCO1_CTL[NMI_NOW]")
-        reg, ba = self.cs.device.get_IO_space("TCOBASE")
-        tcobase = self.cs.register.read_field(reg, ba)
-        return self.cs.hals.Io.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW)
+        # logger().log_hal("[intr] Sending NMI# through TCO1_CTL[NMI_NOW]")
+        # reg, ba = self.cs.device.get_IO_space("TCOBASE")
+        # breakpoint()
+        # tcobase = self.cs.register.read_field(reg, ba)
+        # return self.cs.hals.Io.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW)
+        smbus_instance = self.cs.device.get_obj('8086.SMBUS')
+        if smbus_instance is not None:
+            self.logger.log_hal("[intr] Sending NMI# through TCO1_CTL[NMI_NOW]")
+            try:
+                tcobase, _ = self.cs.hals.IOBAR.get_IO_BAR_base_address("8086.SMBUS.TCOBASE", smbus_instance.instances[0])
+                return self.cs.hals.IOBAR.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW)
+            except CSReadError:
+                self.logger.log("Error finding register 8086.SMBUS.TCOBASE")
+        else:
+                self.logger.log("Unable to find register 8086.SMBUS.TCOBASE")
 
     def find_ACPI_SMI_Buffer(self) -> Optional[UEFI_TABLE.CommBuffInfo]:
         logger().log_hal("Parsing ACPI tables to identify Communication Buffer")

chipsec/hal/common/iobar.py

@@ -33,6 +33,7 @@
 from chipsec.library.logger import logger
 from chipsec.library.exceptions import IOBARNotFoundError
 from chipsec.library.exceptions import CSReadError
+from chipsec.library.registers.io import IO
 
 DEFAULT_IO_BAR_SIZE = 0x100
 
@@ -57,50 +58,50 @@ def is_IO_BAR_defined(self, bar_name: str) -> bool:
     #
     # Get base address of I/O range by IO BAR name
     #
-    def get_IO_BAR_base_address(self, bar_name: str) -> Tuple[int, int]:
-        bar = self.cs.Cfg.IO_BARS[bar_name]
-        if bar is None or bar == {}:
+    def get_IO_BAR_base_address(self, bar_name: str, instance) -> Tuple[int, int]:
+        reglist = self.cs.register.get_list_by_name(bar_name)
+        bar = reglist[0].get_def(bar_name)
+        if not bar:
             raise IOBARNotFoundError(f'IOBARNotFound: {bar_name}')
+        base = 0
+        empmty_base = 0
 
-        if 'register' in bar:
-            bar_reg = bar['register']
-            if 'base_field' in bar:
-                base_field = bar['base_field']
+        if bar.register:
+            if instance is not None:
+                bar_reg = self.cs.register.get_instance_by_name(bar.register, instance)
+            else:
+                bar_reg = self.cs.register.get_list_by_name(bar.register)[0]
+
+            if bar.base_field:
+                base_field = bar.base_field
                 try:
-                    base = self.cs.register.read_field(bar_reg, base_field, preserve_field_position=True)
+                    base = bar_reg.get_field(base_field)
                 except Exception:
-                    base = 0
+                    pass
                 try:
-                    empty_base = self.cs.register.get_field_mask(bar_reg, base_field, preserve_field_position=True)
+                    empty_base = bar_reg.get_field_mask(base_field, True)
                 except Exception:
-                    empty_base = 0
+                    pass
             else:
                 try:
-                    base = self.cs.register.read(bar_reg)
+                    base = bar_reg.read()
                 except Exception:
-                    base = 0
+                    pass
                 try:
-                    empty_base = self.cs.register.get_field_mask(bar_reg, preserve_field_position=True)
+                    empty_base = bar_reg.get_mask()
                 except Exception:
-                    empty_base = 0
-        else:
-            # this method is not preferred
-            base = self.cs.hals.Pci.read_word(self.cs.device.get_first_bus(bar), bar['dev'], bar['fun'], bar['reg'])
-            empty_base = 0xFFFF
-
-        if 'fixed_address' in bar and (base == empty_base or base == 0):
-            base = bar['fixed_address']
-            if logger().HAL:
-                logger().log(f'[iobar] Using fixed address for {bar_name}: 0x{base:016X}')
-
-        if 'mask' in bar:
-            base = base & bar['mask']
-        if 'offset' in bar:
-            base = base + bar['offset']
-        size = bar['size'] if ('size' in bar) else DEFAULT_IO_BAR_SIZE
-
-        if logger().HAL:
-            logger().log(f'[iobar] {bar_name}: 0x{base:04X} (size = 0x{size:X})')
+                    pass
+
+        if bar.fixed_address and (base == empty_base or base == 0):
+            base = bar.fixed_address
+            self.logger.log_hal(f'[iobar] Using fixed address for {bar_name}: 0x{base:016X}')
+
+        if bar.mask:
+            base = base & bar.mask
+        if bar.offset:
+            base = base + bar.offset
+        size = bar.size if bar.size else DEFAULT_IO_BAR_SIZE
+        self.logger.log_hal(f'[iobar] {bar_name}: 0x{base:04X} (size = 0x{size:X})')
         if base == 0:
             raise CSReadError(f'IOBAR ({bar_name}) base address is 0')
         return base, size
@@ -109,12 +110,11 @@ def get_IO_BAR_base_address(self, bar_name: str) -> Tuple[int, int]:
     # Read I/O register from I/O range defined by I/O BAR name
     #
     def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int:
-        if logger().HAL:
-            logger().log(f'[iobar] read {bar_name} + 0x{offset:X} ({size:d})')
+        self.logger.log_hal(f'[iobar] read {bar_name} + 0x{offset:X} ({size:d})')
         (bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
         io_port = bar_base + offset
-        if offset > bar_size and logger().HAL:
-            logger().log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
+        if offset > bar_size and self.logger.HAL:
+            self.logger.log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
         value = self.cs.hals.Io.read(io_port, size)
         return value
 
@@ -123,63 +123,50 @@ def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int:
     #
     def write_IO_BAR_reg(self, bar_name: str, offset: int, size: int, value: int) -> int:
         (bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
-        if logger().HAL:
-            logger().log(f'[iobar] write {bar_name} + 0x{offset:X} ({size:d}): 0x{value:X}')
+        self.logger.log_hal(f'[iobar] write {bar_name} + 0x{offset:X} ({size:d}): 0x{value:X}')
         io_port = bar_base + offset
-        if offset > bar_size and logger().HAL:
-            logger().log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
+        if offset > bar_size and self.logger.HAL:
+            self.logger.log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
         return self.cs.hals.Io.write(io_port, value, size)
 
     #
     # Check if I/O range is enabled by BAR name
     #
     def is_IO_BAR_enabled(self, bar_name: str) -> bool:
-        bar = self.cs.Cfg.IO_BARS[bar_name]
+        if not self.is_IO_BAR_defined(bar_name):
+            return False
+        bar = IO.get_def(bar_name)
         is_enabled = True
-        if 'register' in bar:
-            bar_reg = bar['register']
-            if 'enable_field' in bar:
-                bar_en_field = bar['enable_field']
-                is_enabled = (1 == self.cs.register.read_field(bar_reg, bar_en_field))
+        if bar.register:
+            bar_reg = bar.register
+            if bar.enable_field:
+                bar_en_field = bar.enable_field
+                is_enabled = (1 == bar_reg.read_field(bar_en_field))
         return is_enabled
 
     def list_IO_BARs(self) -> None:
         logger().log('')
         logger().log('--------------------------------------------------------------------------------')
-        logger().log(' I/O Range    | BAR Register   | Base             | Size     | En? | Description')
+        logger().log(f' {"I/O Range":35} | {"B:D.F":7} | {"Base":16} | {"Size":8} | {"En?":3} | Description')
         logger().log('--------------------------------------------------------------------------------')
-        for _bar_name in self.cs.Cfg.IO_BARS:
-            if not self.is_IO_BAR_defined(_bar_name):
-                continue
-            _bar = self.cs.Cfg.IO_BARS[_bar_name]
-            bus_data = []
-            if 'register' in _bar:
-                bus_data = self.cs.register.get_bus(_bar['register'])
-                if not bus_data:
-                    if 'bus' in self.cs.register.get_def(_bar['register']):
-                        bus_data = [self.cs.register.get_def(_bar['register'])['bus']]
-            elif 'bus' in _bar:
-                bus_data.extend(_bar['bus'])
-            else:
-                continue
-
-            for bus in bus_data:
-                try:
-                    (_base, _size) = self.get_IO_BAR_base_address(_bar_name)
-                except CSReadError:
-                    if self.logger.HAL:
-                        self.logger.log(f"Unable to find IO BAR {_bar_name}")
-                    continue
-                _en = self.is_IO_BAR_enabled(_bar_name)
-
-                if 'register' in _bar:
-                    _s = _bar['register']
-                    if 'offset' in _bar:
-                        _s += (f' + 0x{_bar["offset"]:X}')
-                else:
-                    _s = f'{bus:02X}:{_bar["dev"]:02X}.{_bar["fun"]:01X} + {_bar["reg"]}'
-
-                logger().log(f' {_bar_name:12} | {_s:14} | {_base:016X} | {_size:08X} | {_en:d}   | {_bar["desc"]}')
+        for vid in self.cs.Cfg.IO_BARS:
+            for dev in self.cs.Cfg.IO_BARS[vid]:
+                for _bar_name in self.cs.Cfg.IO_BARS[vid][dev]:
+                    bar_name = f'{vid}.{dev}.{_bar_name}'
+                    if not self.is_IO_BAR_defined(bar_name):
+                        continue
+                    _bar = self.cs.Cfg.IO_BARS[vid][dev][_bar_name]
+
+                    for instance in _bar.instances:
+                        (_base, _size) = _bar.get_base(instance)
+                        if _base is None:
+                            (_base, _size) = self.get_IO_BAR_base_address(bar_name, instance)
+                        _en = self.is_IO_BAR_enabled(bar_name, instance)
+                        if instance.bus is not None:
+                            bdf = f'{instance.bus:02X}:{instance.dev:02X}.{instance.fun:1X}'
+                        else:
+                            bdf = 'fixed'
+                        logger().log(f' {_bar_name:35} | {bdf:7} | {_base:016X} | {_size:08X} | {_en:d}   | {_bar["desc"]}')
 
     #
     # Read I/O range by I/O BAR name
@@ -199,10 +186,10 @@ def dump_IO_BAR(self, bar_name: str, size: int = 1) -> None:
         (range_base, range_size) = self.get_IO_BAR_base_address(bar_name)
         n = range_size // size
         fmt = f'0{size * 2:d}X'
-        logger().log(f"[iobar] I/O BAR {bar_name}:")
+        self.logger.log(f"[iobar] I/O BAR {bar_name}:")
         for i in range(n):
             reg = self.cs.hals.Io.read(range_base + i * size, size)
-            logger().log(f'{size * i:+04X}: {reg:{fmt}}')
+            self.logger.log(f'{size * i:+04X}: {reg:{fmt}}')
 
 
 haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': ['IOBAR']}

chipsec/hal/common/mmio.py

@@ -295,7 +295,6 @@ def get_MMIO_BAR_base_address(self, bar_name: str, pciobj: Optional[int] = None)
             size = DEFAULT_MMIO_BAR_SIZE
         self.logger.log_hal('[mmio] {}: 0x{:016X} (size = 0x{:X})'.format(bar_name, base, size))
         if base == 0:
-            breakpoint()
             self.logger.log_hal('[mmio] Base address was determined to be 0.')
             raise CSReadError('[mmio] Base address was determined to be 0')
 

chipsec/hal/common/pci.py

@@ -358,4 +358,4 @@ def is_enabled(self, bus: int, dev: int, fun: int) -> bool:
             return False
         return True
 
-haldata = {"arch":[HALBase.MfgIds.Any, HALBase.MfgIds.Intel], 'name': ['Pci']} #change arch to CPUID genuine intel/amd
+haldata = {"arch":[HALBase.MfgIds.Any, HALBase.MfgIds.Intel], 'name': ['Pci']}

chipsec/hal/intel/cpu.py

@@ -240,4 +240,4 @@ def dump_page_tables_all(self) -> None:
             self.dump_page_tables(cr3)
 
 
-haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': ['CPU']} #change arch to CPUID genuine intel/amd
+haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': ['CPU']}

chipsec/library/device.py

@@ -90,7 +90,6 @@ def get_bus(self, device_name: str) -> List[int]:
         """Retrieves bus value(s) from PCI device"""
         dev_list = self.get_objlist(device_name)
         buses = []
-        breakpoint()
         for dev in dev_list:
             for instance_key in dev.instances.keys():
                 buses.append(dev.instances[instance_key].bus)

tests/utilcmd/run_chipsec_util.py

@@ -54,6 +54,7 @@ def setup_run_destroy_util_get_log_output(init_replay_file: str, util_name: str,
     replayHelper = rph.ReplayHelper(init_replay_file)
     csu._helper = replayHelper
     retval = run_chipsec_util(csu, util_replay_file)
+    clear_cs()
     logger_calls = []
     for func in logging_fucntions_to_capture:
         if hasattr(chipsec.library.logger._logger, func):