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Update configs and files for some external tests
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1 parent 6d27c8b commit 90365f7

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7 files changed

+31
-18
lines changed

7 files changed

+31
-18
lines changed

‎chipsec/cfg/8086/HOSTCTL/hostctl11gen.xml‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,6 @@
11
<?xml version="1.0"?>
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<configuration>
33

4-
<mmio>
5-
<bar name="PXPEPBAR" register="PXPEPBAR" base_field="PXPEPBAR" size="0x1000" enable_bit="0" desc="PCI Express Egress Port Register Range"/>
6-
<bar name="MCHBAR" register="MCHBAR" base_field="MCHBAR" size="0x8000" enable_bit="0" desc="Host Memory Mapped Register Range"/>
7-
<bar name="MMCFG" register="PCIEXBAR" base_field="PXPEPBAR" size="0x1000" enable_bit="0" desc="PCI Express Register Range"/>
8-
<bar name="DMIBAR" register="DMIBAR" base_field="DMIBAR" size="0x1000" enable_bit="0" desc="Root Complex Register Range"/>
9-
<!-- VT-d BARs -->
10-
<bar name="VTBAR" register="VTBAR" base_field="Base" size="0x1000" enable_field="Enable" desc="Intel VT-d Register Register Range"/>
11-
<bar name="GFXVTBAR" register="GFXVTBAR" base_field="Base" size="0x1000" enable_field="Enable" desc="Intel Processor Graphics VT-d Register Range"/>
12-
</mmio>
13-
144
<!-- #################################### -->
155
<!-- -->
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<!-- Configuration registers -->

‎chipsec/cfg/8086/MMIO/pwrm0.xml‎

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,10 @@
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<field name="SCIS" bit="0" size="3" desc="SCI IRQ Select"/>
1212
</register>
1313
<register name="PM_CFG" type="mmio" bar="PWRMBASE" offset="0x1818" size="4" desc="Power Management Configuration Reg 1"/>
14+
<register name="ETR3" type="mmio" bar="PWRMBASE" offset="0x1048" size="4" desc="Extended Test Mode Register 3">
15+
<field name="CF9GR" bit="20" size="1" desc="CF9h Global Reset"/>
16+
<field name="CF9LOCK" bit="31" size="1" desc="CF9h Lock"/>
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</register>
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</registers>
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1620
<controls>

‎chipsec/cfg/8086/MSR/msr2.xml‎

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Original file line numberDiff line numberDiff line change
@@ -134,6 +134,19 @@
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<field name="EB_LEG_BITMAP_BASE" bit="12" size="52" desc="Linear address bits of legacy code page bitmap" />
135135
</register>
136136

137+
<register name="MSR_PKG_CST_CONFIG_CONTROL" type="msr" scope="core" msr="0xE2" desc="C-State Configuration Register">
138+
<field name="LOCK" bit="15" size="1" desc="Lock MSR_PKG_CST_CONFIG_CONTROL register" />
139+
<field name="Reserved2" bit="11" size="4" desc="Reserved" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
140+
<field name="IO_MWIAT_REDIRECTION" bit="10" size="1" desc="map IO_read to PMG_IO_BASE_ADDRBASE + offset to MWAIT" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
141+
<field name="Reserved" bit="4" size="6" desc="Reserved" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
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<field name="MAX_PKG_C_STATE" bit="0" size="4" desc="Lowest C-state for the package" lockedby="MSR_PKG_CST_CONFIG_CONTROL.LOCK"/>
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</register>
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<register name="FEATURE_CONFIG" type="msr" msr="0x13C" scope="core" desc="FEATURE_CONFIG Register">
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<field name="AES_DISABLE" bit="1" size="1" desc="Disable AES on Core" lockedby="FEATURE_CONFIG.Lock"/>
147+
<field name="Lock" bit="0" size="1" desc="FEATURE_CONFIG Register Lock" />
148+
</register>
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137150
</registers>
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<controls>

‎chipsec/cfg/8086/tglu.xml‎

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Original file line numberDiff line numberDiff line change
@@ -49,7 +49,9 @@ http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.
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<!-- -->
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<!-- #################################### -->
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<pci>
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<device name="HOSTCTL" bus="0x0" dev="0x00" fun="0" did="0x9A14" config="HOSTCTL.hostctl11gen.xml"/>
52+
<device name="HOSTCTL" bus="0x0" dev="0x00" fun="0" did="0x9A14" config="HOSTCTL.hostctl11gen.xml">
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<subcomponent type="mmiobar" name="MCHBAR" register="MCHBAR" base_field="MCHBAR" size="0x8000" enable_bit="0" config="MMIO.mmio0.xml" />
54+
</device>
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<!-- <device name="HOSTCTL" bus="0x0" dev="0x00" fun="0" config="IOMMU.iommu.xml"/> -->
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<device name="IGD" bus="0x0" dev="0x02" fun="0" config="IGD.igd0.xml"/>
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<device name="MEI1" bus="0x0" dev="0x16" fun="0" config="ME.mei0.xml" />

‎chipsec/library/register.py‎

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Original file line numberDiff line numberDiff line change
@@ -337,12 +337,10 @@ def has_field(self, reg_name: str, field_name: str) -> bool:
337337
reg_defs = self.cs.Cfg.get_reglist(reg_name)
338338
except RegisterNotFoundError:
339339
return False
340-
for reg_def in reg_defs:
341-
try:
342-
return field_name in reg_def.fields
343-
except KeyError:
344-
return False
345-
return False
340+
try:
341+
return bool(reg_defs) and all([field_name in reg_def.fields for reg_def in reg_defs])
342+
except KeyError:
343+
return False
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347345
def get_match(self, name: str) -> List[str]:
348346
"""

‎tests/modules/tgl/common-remap_test.json‎

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@@ -31,6 +31,12 @@
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],
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"(4275851416,8)": [
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"0"
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],
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"(4275886224,8)": [
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"549754765312"
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],
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"(4275886232,8)": [
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"0"
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]
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},
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"read_msr": {

‎tests/modules/tgl/enumeration.json‎

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@@ -132,7 +132,7 @@
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},
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"read_pci_reg": {
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"(0,0,0,0,4)": [
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"1493467270"
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"2585034886"
136136
],
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"(0,0,0,8,1)": [
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"1"

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