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Commit 50318bf

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James Munnshannobraun
authored andcommitted
Update to be compatible with RTFM
1 parent fd91557 commit 50318bf

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2 files changed

+16
-8
lines changed

2 files changed

+16
-8
lines changed

nrf52-hal-common/src/rtc.rs

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ where
8282
}
8383

8484
/// Enable the generation of a hardware interrupt from a given stimulus
85-
pub fn enable_interrupt(&mut self, int: RtcInterrupt, nvic: &mut NVIC) {
85+
pub fn enable_interrupt(&mut self, int: RtcInterrupt, nvic: Option<&mut NVIC>) {
8686
match int {
8787
RtcInterrupt::Tick => self.periph.intenset.write(|w| w.tick().set()),
8888
RtcInterrupt::Overflow => self.periph.intenset.write(|w| w.ovrflw().set()),
@@ -91,11 +91,13 @@ where
9191
RtcInterrupt::Compare2 => self.periph.intenset.write(|w| w.compare2().set()),
9292
RtcInterrupt::Compare3 => self.periph.intenset.write(|w| w.compare3().set()),
9393
}
94-
nvic.enable(T::INTERRUPT);
94+
if let Some(nvic) = nvic {
95+
nvic.enable(T::INTERRUPT);
96+
}
9597
}
9698

9799
/// Disable the generation of a hardware interrupt from a given stimulus
98-
pub fn disable_interrupt(&mut self, int: RtcInterrupt, nvic: &mut NVIC) {
100+
pub fn disable_interrupt(&mut self, int: RtcInterrupt, nvic: Option<&mut NVIC>) {
99101
match int {
100102
RtcInterrupt::Tick => self.periph.intenclr.write(|w| w.tick().clear()),
101103
RtcInterrupt::Overflow => self.periph.intenclr.write(|w| w.ovrflw().clear()),
@@ -104,7 +106,9 @@ where
104106
RtcInterrupt::Compare2 => self.periph.intenclr.write(|w| w.compare2().clear()),
105107
RtcInterrupt::Compare3 => self.periph.intenclr.write(|w| w.compare3().clear()),
106108
}
107-
nvic.disable(T::INTERRUPT);
109+
if let Some(nvic) = nvic {
110+
nvic.disable(T::INTERRUPT);
111+
}
108112
}
109113

110114
/// Enable the generation of a hardware event from a given stimulus

nrf52-hal-common/src/timer.rs

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,26 +60,30 @@ where
6060
///
6161
/// Enables an interrupt that is fired when the timer reaches the value that
6262
/// is given as an argument to `start`.
63-
pub fn enable_interrupt(&mut self, nvic: &mut NVIC) {
63+
pub fn enable_interrupt(&mut self, nvic: Option<&mut NVIC>) {
6464
// As of this writing, the timer code only uses
6565
// `cc[0]`/`events_compare[0]`. If the code is extended to use other
6666
// compare registers, the following needs to be adapted.
6767
self.0.intenset.modify(|_, w| w.compare0().set());
6868

69-
nvic.enable(T::INTERRUPT);
69+
if let Some(nvic) = nvic {
70+
nvic.enable(T::INTERRUPT);
71+
}
7072
}
7173

7274
/// Disables the interrupt for this timer
7375
///
7476
/// Disables an interrupt that is fired when the timer reaches the value
7577
/// that is given as an argument to `start`.
76-
pub fn disable_interrupt(&mut self, nvic: &mut NVIC) {
78+
pub fn disable_interrupt(&mut self, nvic: Option<&mut NVIC>) {
7779
// As of this writing, the timer code only uses
7880
// `cc[0]`/`events_compare[0]`. If the code is extended to use other
7981
// compare registers, the following needs to be adapted.
8082
self.0.intenclr.modify(|_, w| w.compare0().clear());
8183

82-
nvic.disable(T::INTERRUPT);
84+
if let Some(nvic) = nvic {
85+
nvic.disable(T::INTERRUPT);
86+
}
8387
}
8488

8589
pub fn delay(&mut self, cycles: u32) {

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