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}
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/// Enable the generation of a hardware interrupt from a given stimulus
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- pub fn enable_interrupt ( & mut self , int : RtcInterrupt , nvic : & mut NVIC ) {
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+ pub fn enable_interrupt ( & mut self , int : RtcInterrupt , nvic : Option < & mut NVIC > ) {
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match int {
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RtcInterrupt :: Tick => self . periph . intenset . write ( |w| w. tick ( ) . set ( ) ) ,
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RtcInterrupt :: Overflow => self . periph . intenset . write ( |w| w. ovrflw ( ) . set ( ) ) ,
@@ -91,11 +91,13 @@ where
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RtcInterrupt :: Compare2 => self . periph . intenset . write ( |w| w. compare2 ( ) . set ( ) ) ,
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RtcInterrupt :: Compare3 => self . periph . intenset . write ( |w| w. compare3 ( ) . set ( ) ) ,
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}
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- nvic. enable ( T :: INTERRUPT ) ;
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+ if let Some ( nvic) = nvic {
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+ nvic. enable ( T :: INTERRUPT ) ;
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+ }
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}
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/// Disable the generation of a hardware interrupt from a given stimulus
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- pub fn disable_interrupt ( & mut self , int : RtcInterrupt , nvic : & mut NVIC ) {
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+ pub fn disable_interrupt ( & mut self , int : RtcInterrupt , nvic : Option < & mut NVIC > ) {
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match int {
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RtcInterrupt :: Tick => self . periph . intenclr . write ( |w| w. tick ( ) . clear ( ) ) ,
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RtcInterrupt :: Overflow => self . periph . intenclr . write ( |w| w. ovrflw ( ) . clear ( ) ) ,
@@ -104,7 +106,9 @@ where
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RtcInterrupt :: Compare2 => self . periph . intenclr . write ( |w| w. compare2 ( ) . clear ( ) ) ,
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RtcInterrupt :: Compare3 => self . periph . intenclr . write ( |w| w. compare3 ( ) . clear ( ) ) ,
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}
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- nvic. disable ( T :: INTERRUPT ) ;
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+ if let Some ( nvic) = nvic {
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+ nvic. disable ( T :: INTERRUPT ) ;
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+ }
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}
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/// Enable the generation of a hardware event from a given stimulus
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