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lulfhargoniX
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Move into parent module
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nrf-hal-common/src/uarte.rs

Lines changed: 94 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@ use core::fmt;
88
use core::ops::Deref;
99
use core::sync::atomic::{compiler_fence, Ordering::SeqCst};
1010

11+
use embedded_hal::blocking::serial as bserial;
1112
use embedded_hal::digital::v2::OutputPin;
13+
use embedded_hal::serial;
14+
15+
use nb;
1216

1317
#[cfg(any(feature = "52833", feature = "52840"))]
1418
use crate::pac::UARTE1;
@@ -596,128 +600,120 @@ where
596600
}
597601
}
598602

599-
/// Implementation of the embedded_hal::serial::* and embedded_hal::blocking::serial::* traits for UartTx and UartRx.
600-
pub mod serial {
601-
use super::*;
602-
use embedded_hal::blocking::serial as bserial;
603-
use embedded_hal::serial;
604-
use nb;
605-
606-
impl<T> serial::Write<u8> for UarteTx<T>
607-
where
608-
T: Instance,
609-
{
610-
type Error = Error;
611-
612-
/// Write a single byte to the internal buffer. Returns nb::Error::WouldBlock if buffer is full.
613-
fn write(&mut self, b: u8) -> nb::Result<(), Self::Error> {
614-
let uarte = unsafe { &*T::ptr() };
603+
impl<T> serial::Write<u8> for UarteTx<T>
604+
where
605+
T: Instance,
606+
{
607+
type Error = Error;
615608

616-
// Prevent writing to buffer while DMA transfer is in progress.
617-
if uarte.events_txstarted.read().bits() == 1 {
618-
return Err(nb::Error::WouldBlock);
619-
}
609+
/// Write a single byte to the internal buffer. Returns nb::Error::WouldBlock if buffer is full.
610+
fn write(&mut self, b: u8) -> nb::Result<(), Self::Error> {
611+
let uarte = unsafe { &*T::ptr() };
620612

621-
if self.written < self.tx_buf.len() {
622-
self.tx_buf[self.written] = b;
623-
self.written += 1;
624-
Ok(())
625-
} else {
626-
Err(nb::Error::WouldBlock)
627-
}
613+
// Prevent writing to buffer while DMA transfer is in progress.
614+
if uarte.events_txstarted.read().bits() == 1 {
615+
return Err(nb::Error::WouldBlock);
628616
}
629617

630-
/// Flush the TX buffer non-blocking. Returns nb::Error::WouldBlock if not yet flushed.
631-
fn flush(&mut self) -> nb::Result<(), Self::Error> {
632-
let uarte = unsafe { &*T::ptr() };
633-
634-
// If txstarted is set, we are in the process of transmitting.
635-
let in_progress = uarte.events_txstarted.read().bits() == 1;
636-
637-
if in_progress {
638-
let endtx = uarte.events_endtx.read().bits() != 0;
639-
let txstopped = uarte.events_txstopped.read().bits() != 0;
640-
if endtx || txstopped {
641-
// We are done, cleanup the state.
642-
uarte.events_txstarted.reset();
643-
self.written = 0;
644-
645-
// Conservative compiler fence to prevent optimizations that do not
646-
// take in to account actions by DMA. The fence has been placed here,
647-
// after all possible DMA actions have completed.
648-
compiler_fence(SeqCst);
618+
if self.written < self.tx_buf.len() {
619+
self.tx_buf[self.written] = b;
620+
self.written += 1;
621+
Ok(())
622+
} else {
623+
Err(nb::Error::WouldBlock)
624+
}
625+
}
649626

650-
if txstopped {
651-
return Err(nb::Error::Other(Error::Transmit));
652-
}
627+
/// Flush the TX buffer non-blocking. Returns nb::Error::WouldBlock if not yet flushed.
628+
fn flush(&mut self) -> nb::Result<(), Self::Error> {
629+
let uarte = unsafe { &*T::ptr() };
653630

654-
// Lower power consumption by disabling the transmitter once we're
655-
// finished.
656-
stop_write(uarte);
631+
// If txstarted is set, we are in the process of transmitting.
632+
let in_progress = uarte.events_txstarted.read().bits() == 1;
657633

658-
compiler_fence(SeqCst);
659-
Ok(())
660-
} else {
661-
// Still not done, don't block.
662-
Err(nb::Error::WouldBlock)
663-
}
664-
} else {
665-
// No need to trigger transmit if we don't have anything written
666-
if self.written == 0 {
667-
return Ok(());
634+
if in_progress {
635+
let endtx = uarte.events_endtx.read().bits() != 0;
636+
let txstopped = uarte.events_txstopped.read().bits() != 0;
637+
if endtx || txstopped {
638+
// We are done, cleanup the state.
639+
uarte.events_txstarted.reset();
640+
self.written = 0;
641+
642+
// Conservative compiler fence to prevent optimizations that do not
643+
// take in to account actions by DMA. The fence has been placed here,
644+
// after all possible DMA actions have completed.
645+
compiler_fence(SeqCst);
646+
647+
if txstopped {
648+
return Err(nb::Error::Other(Error::Transmit));
668649
}
669650

670-
start_write(uarte, &self.tx_buf[0..self.written]);
651+
// Lower power consumption by disabling the transmitter once we're
652+
// finished.
653+
stop_write(uarte);
671654

655+
compiler_fence(SeqCst);
656+
Ok(())
657+
} else {
658+
// Still not done, don't block.
672659
Err(nb::Error::WouldBlock)
673660
}
661+
} else {
662+
// No need to trigger transmit if we don't have anything written
663+
if self.written == 0 {
664+
return Ok(());
665+
}
666+
667+
start_write(uarte, &self.tx_buf[0..self.written]);
668+
669+
Err(nb::Error::WouldBlock)
674670
}
675671
}
672+
}
676673

677-
// Auto-implement the blocking variant
678-
impl<T> bserial::write::Default<u8> for UarteTx<T> where T: Instance {}
674+
// Auto-implement the blocking variant
675+
impl<T> bserial::write::Default<u8> for UarteTx<T> where T: Instance {}
679676

680-
impl<T> core::fmt::Write for UarteTx<T>
681-
where
682-
T: Instance,
683-
{
684-
fn write_str(&mut self, s: &str) -> fmt::Result {
685-
s.as_bytes()
686-
.iter()
687-
.try_for_each(|c| nb::block!(self.write(*c)))
688-
.map_err(|_| core::fmt::Error)
689-
}
677+
impl<T> core::fmt::Write for UarteTx<T>
678+
where
679+
T: Instance,
680+
{
681+
fn write_str(&mut self, s: &str) -> fmt::Result {
682+
s.as_bytes()
683+
.iter()
684+
.try_for_each(|c| nb::block!(self.write(*c)))
685+
.map_err(|_| core::fmt::Error)
690686
}
687+
}
691688

692-
impl<T> serial::Read<u8> for UarteRx<T>
693-
where
694-
T: Instance,
695-
{
696-
type Error = Error;
697-
fn read(&mut self) -> nb::Result<u8, Self::Error> {
698-
let uarte = unsafe { &*T::ptr() };
689+
impl<T> serial::Read<u8> for UarteRx<T>
690+
where
691+
T: Instance,
692+
{
693+
type Error = Error;
694+
fn read(&mut self) -> nb::Result<u8, Self::Error> {
695+
let uarte = unsafe { &*T::ptr() };
699696

700-
compiler_fence(SeqCst);
697+
compiler_fence(SeqCst);
701698

702-
let in_progress = uarte.events_rxstarted.read().bits() == 1;
703-
if in_progress && uarte.events_endrx.read().bits() == 0 {
704-
return Err(nb::Error::WouldBlock);
705-
}
699+
let in_progress = uarte.events_rxstarted.read().bits() == 1;
700+
if in_progress && uarte.events_endrx.read().bits() == 0 {
701+
return Err(nb::Error::WouldBlock);
702+
}
706703

707-
if in_progress {
708-
let b = self.rx_buf[0];
709-
uarte.events_rxstarted.write(|w| w);
704+
if in_progress {
705+
let b = self.rx_buf[0];
706+
uarte.events_rxstarted.write(|w| w);
710707

711-
finalize_read(uarte);
708+
finalize_read(uarte);
712709

713-
if uarte.rxd.amount.read().bits() != 1 as u32 {
714-
return Err(nb::Error::Other(Error::Receive));
715-
}
716-
Ok(b)
717-
} else {
718-
start_read(&uarte, self.rx_buf)?;
719-
Err(nb::Error::WouldBlock)
710+
if uarte.rxd.amount.read().bits() != 1 as u32 {
711+
return Err(nb::Error::Other(Error::Receive));
720712
}
713+
Ok(b)
714+
} else {
715+
start_read(&uarte, self.rx_buf)?;
716+
Err(nb::Error::WouldBlock)
721717
}
722718
}
723719
}

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