Also release owned Pins with Usart::free()

Author: timokroeger

nrf-hal-common/src/uarte.rs

@@ -36,7 +36,10 @@ pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
 ///   are disabled before using `Uarte`. See product specification:
 ///     - nrf52832: Section 15.2
 ///     - nrf52840: Section 6.1.2
-pub struct Uarte<T>(T);
+pub struct Uarte<T> {
+    uarte: T,
+    pins: Pins,
+}
 
 impl<T> Uarte<T>
 where
@@ -93,7 +96,7 @@ where
         // Configure frequency.
         uarte.baudrate.write(|w| w.baudrate().variant(baudrate));
 
-        Uarte(uarte)
+        Uarte { uarte, pins }
     }
 
     /// Write via UARTE.
@@ -116,19 +119,19 @@ where
         compiler_fence(SeqCst);
 
         // Reset the events.
-        self.0.events_endtx.reset();
-        self.0.events_txstopped.reset();
+        self.uarte.events_endtx.reset();
+        self.uarte.events_txstopped.reset();
 
         // Set up the DMA write.
-        self.0.txd.ptr.write(|w|
+        self.uarte.txd.ptr.write(|w|
             // We're giving the register a pointer to the stack. Since we're
             // waiting for the UARTE transaction to end before this stack pointer
             // becomes invalid, there's nothing wrong here.
             //
             // The PTR field is a full 32 bits wide and accepts the full range
             // of values.
             unsafe { w.ptr().bits(tx_buffer.as_ptr() as u32) });
-        self.0.txd.maxcnt.write(|w|
+        self.uarte.txd.maxcnt.write(|w|
             // We're giving it the length of the buffer, so no danger of
             // accessing invalid memory. We have verified that the length of the
             // buffer fits in an `u8`, so the cast to `u8` is also fine.
@@ -138,16 +141,16 @@ where
             unsafe { w.maxcnt().bits(tx_buffer.len() as _) });
 
         // Start UARTE Transmit transaction.
-        self.0.tasks_starttx.write(|w|
+        self.uarte.tasks_starttx.write(|w|
             // `1` is a valid value to write to task registers.
             unsafe { w.bits(1) });
 
         // Wait for transmission to end.
         let mut endtx;
         let mut txstopped;
         loop {
-            endtx = self.0.events_endtx.read().bits() != 0;
-            txstopped = self.0.events_txstopped.read().bits() != 0;
+            endtx = self.uarte.events_endtx.read().bits() != 0;
+            txstopped = self.uarte.events_txstopped.read().bits() != 0;
             if endtx || txstopped {
                 break;
             }
@@ -164,7 +167,7 @@ where
 
         // Lower power consumption by disabling the transmitter once we're
         // finished.
-        self.0.tasks_stoptx.write(|w|
+        self.uarte.tasks_stoptx.write(|w|
             // `1` is a valid value to write to task registers.
             unsafe { w.bits(1) });
 
@@ -181,11 +184,11 @@ where
         self.start_read(rx_buffer)?;
 
         // Wait for transmission to end.
-        while self.0.events_endrx.read().bits() == 0 {}
+        while self.uarte.events_endrx.read().bits() == 0 {}
 
         self.finalize_read();
 
-        if self.0.rxd.amount.read().bits() != rx_buffer.len() as u32 {
+        if self.uarte.rxd.amount.read().bits() != rx_buffer.len() as u32 {
             return Err(Error::Receive);
         }
 
@@ -226,7 +229,7 @@ where
         let mut timeout_occured = false;
 
         loop {
-            event_complete |= self.0.events_endrx.read().bits() != 0;
+            event_complete |= self.uarte.events_endrx.read().bits() != 0;
             timeout_occured |= timer.wait().is_ok();
             if event_complete || timeout_occured {
                 break;
@@ -241,7 +244,7 @@ where
         // Cleanup, even in the error case.
         self.finalize_read();
 
-        let bytes_read = self.0.rxd.amount.read().bits() as usize;
+        let bytes_read = self.uarte.rxd.amount.read().bits() as usize;
 
         if timeout_occured && !event_complete {
             return Err(Error::Timeout(bytes_read));
@@ -272,15 +275,15 @@ where
         compiler_fence(SeqCst);
 
         // Set up the DMA read
-        self.0.rxd.ptr.write(|w|
+        self.uarte.rxd.ptr.write(|w|
             // We're giving the register a pointer to the stack. Since we're
             // waiting for the UARTE transaction to end before this stack pointer
             // becomes invalid, there's nothing wrong here.
             //
             // The PTR field is a full 32 bits wide and accepts the full range
             // of values.
             unsafe { w.ptr().bits(rx_buffer.as_ptr() as u32) });
-        self.0.rxd.maxcnt.write(|w|
+        self.uarte.rxd.maxcnt.write(|w|
             // We're giving it the length of the buffer, so no danger of
             // accessing invalid memory. We have verified that the length of the
             // buffer fits in an `u8`, so the cast to `u8` is also fine.
@@ -290,7 +293,7 @@ where
             unsafe { w.maxcnt().bits(rx_buffer.len() as _) });
 
         // Start UARTE Receive transaction.
-        self.0.tasks_startrx.write(|w|
+        self.uarte.tasks_startrx.write(|w|
             // `1` is a valid value to write to task registers.
             unsafe { w.bits(1) });
 
@@ -300,7 +303,7 @@ where
     /// Finalize a UARTE read transaction by clearing the event.
     fn finalize_read(&mut self) {
         // Reset the event, otherwise it will always read `1` from now on.
-        self.0.events_endrx.write(|w| w);
+        self.uarte.events_endrx.write(|w| w);
 
         // Conservative compiler fence to prevent optimizations that do not
         // take in to account actions by DMA. The fence has been placed here,
@@ -311,26 +314,26 @@ where
     /// Stop an unfinished UART read transaction and flush FIFO to DMA buffer.
     fn cancel_read(&mut self) {
         // Stop reception.
-        self.0.tasks_stoprx.write(|w| unsafe { w.bits(1) });
+        self.uarte.tasks_stoprx.write(|w| unsafe { w.bits(1) });
 
         // Wait for the reception to have stopped.
-        while self.0.events_rxto.read().bits() == 0 {}
+        while self.uarte.events_rxto.read().bits() == 0 {}
 
         // Reset the event flag.
-        self.0.events_rxto.write(|w| w);
+        self.uarte.events_rxto.write(|w| w);
 
         // Ask UART to flush FIFO to DMA buffer.
-        self.0.tasks_flushrx.write(|w| unsafe { w.bits(1) });
+        self.uarte.tasks_flushrx.write(|w| unsafe { w.bits(1) });
 
         // Wait for the flush to complete.
-        while self.0.events_endrx.read().bits() == 0 {}
+        while self.uarte.events_endrx.read().bits() == 0 {}
 
         // The event flag itself is later reset by `finalize_read`.
     }
 
     /// Return the raw interface to the underlying UARTE peripheral.
-    pub fn free(self) -> T {
-        self.0
+    pub fn free(self) -> (T, Pins) {
+        (self.uarte, self.pins)
     }
 }