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| 1 | +#![no_std] |
| 2 | +#![no_main] |
| 3 | + |
| 4 | +// Demo of using non-blocking DMA transactions with the |
| 5 | +// TWIS (Two Wire Interface/I2C in peripheral mode) module. |
| 6 | + |
| 7 | +use { |
| 8 | + core::{ |
| 9 | + panic::PanicInfo, |
| 10 | + sync::atomic::{compiler_fence, Ordering}, |
| 11 | + }, |
| 12 | + hal::{gpio::p0::Parts, gpiote::Gpiote, pac::TWIS0, twis::*}, |
| 13 | + nrf52840_hal as hal, |
| 14 | + rtt_target::{rprintln, rtt_init_print}, |
| 15 | +}; |
| 16 | + |
| 17 | +type DmaBuffer = &'static mut [u8; 8]; |
| 18 | + |
| 19 | +pub enum TwisTransfer { |
| 20 | + Running(Transfer<TWIS0, DmaBuffer>), |
| 21 | + Idle((DmaBuffer, Twis<TWIS0>)), |
| 22 | +} |
| 23 | + |
| 24 | +#[rtic::app(device = crate::hal::pac, peripherals = true)] |
| 25 | +const APP: () = { |
| 26 | + struct Resources { |
| 27 | + gpiote: Gpiote, |
| 28 | + transfer: Option<TwisTransfer>, |
| 29 | + } |
| 30 | + |
| 31 | + #[init] |
| 32 | + fn init(ctx: init::Context) -> init::LateResources { |
| 33 | + static mut BUF: [u8; 8] = [0; 8]; |
| 34 | + let _clocks = hal::clocks::Clocks::new(ctx.device.CLOCK).enable_ext_hfosc(); |
| 35 | + rtt_init_print!(); |
| 36 | + rprintln!("Waiting for commands from controller..."); |
| 37 | + |
| 38 | + let p0 = Parts::new(ctx.device.P0); |
| 39 | + let scl = p0.p0_14.into_floating_input().degrade(); |
| 40 | + let sda = p0.p0_16.into_floating_input().degrade(); |
| 41 | + |
| 42 | + let twis = Twis::new(ctx.device.TWIS0, Pins { scl, sda }, 0x1A); |
| 43 | + twis.enable_interrupt(TwiEvent::Write) |
| 44 | + .enable_interrupt(TwiEvent::Read) |
| 45 | + .enable_interrupt(TwiEvent::Stopped) |
| 46 | + .enable(); |
| 47 | + |
| 48 | + let btn = p0.p0_29.into_pullup_input().degrade(); |
| 49 | + let gpiote = Gpiote::new(ctx.device.GPIOTE); |
| 50 | + gpiote.port().input_pin(&btn).low(); |
| 51 | + gpiote.port().enable_interrupt(); |
| 52 | + |
| 53 | + init::LateResources { |
| 54 | + gpiote, |
| 55 | + transfer: Some(TwisTransfer::Idle((BUF, twis))), |
| 56 | + } |
| 57 | + } |
| 58 | + |
| 59 | + #[task(binds = GPIOTE, resources = [gpiote, transfer])] |
| 60 | + fn on_gpiote(ctx: on_gpiote::Context) { |
| 61 | + ctx.resources.gpiote.reset_events(); |
| 62 | + rprintln!("Reset buffer"); |
| 63 | + let transfer = ctx.resources.transfer; |
| 64 | + let (buf, twis) = match transfer.take().unwrap() { |
| 65 | + TwisTransfer::Running(t) => t.wait(), |
| 66 | + TwisTransfer::Idle(t) => t, |
| 67 | + }; |
| 68 | + buf.copy_from_slice(&[0; 8][..]); |
| 69 | + rprintln!("{:?}", buf); |
| 70 | + transfer.replace(TwisTransfer::Idle((buf, twis))); |
| 71 | + } |
| 72 | + |
| 73 | + #[task(binds = SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, resources = [transfer])] |
| 74 | + fn on_twis(ctx: on_twis::Context) { |
| 75 | + let transfer = ctx.resources.transfer; |
| 76 | + let (buf, twis) = match transfer.take().unwrap() { |
| 77 | + TwisTransfer::Running(t) => t.wait(), |
| 78 | + TwisTransfer::Idle(t) => t, |
| 79 | + }; |
| 80 | + if twis.is_event_triggered(TwiEvent::Read) { |
| 81 | + twis.reset_event(TwiEvent::Read); |
| 82 | + rprintln!("READ command received"); |
| 83 | + let tx = twis.tx(buf).unwrap(); |
| 84 | + transfer.replace(TwisTransfer::Running(tx)); |
| 85 | + } else if twis.is_event_triggered(TwiEvent::Write) { |
| 86 | + twis.reset_event(TwiEvent::Write); |
| 87 | + rprintln!("WRITE command received"); |
| 88 | + let rx = twis.rx(buf).unwrap(); |
| 89 | + transfer.replace(TwisTransfer::Running(rx)); |
| 90 | + } else { |
| 91 | + twis.reset_event(TwiEvent::Stopped); |
| 92 | + rprintln!("{:?}", buf); |
| 93 | + transfer.replace(TwisTransfer::Idle((buf, twis))); |
| 94 | + } |
| 95 | + } |
| 96 | +}; |
| 97 | + |
| 98 | +#[inline(never)] |
| 99 | +#[panic_handler] |
| 100 | +fn panic(info: &PanicInfo) -> ! { |
| 101 | + cortex_m::interrupt::disable(); |
| 102 | + rprintln!("{}", info); |
| 103 | + loop { |
| 104 | + compiler_fence(Ordering::SeqCst); |
| 105 | + } |
| 106 | +} |
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