@@ -260,7 +260,7 @@ impl<'c> Radio<'c> {
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}
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/// Sample the received signal power (i.e. the presence of possibly interfering signals)
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- /// within the bandwidth of the currently used channel for sample_cycles iterations.
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+ /// within the bandwidth of the currently used channel for ` sample_cycles` iterations.
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/// Note that one iteration has a sample time of 128μs, and that each iteration produces the
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/// average RSSI value measured during this sample time.
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///
@@ -294,14 +294,14 @@ impl<'c> Radio<'c> {
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self . radio . events_edend . reset ( ) ;
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// note that since we have increased EDCNT, the EDSAMPLE register contains the
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- // maximumrecorded value, not the average
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+ // maximum recorded value, not the average
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let read_lvl = self . radio . edsample . read ( ) . edlvl ( ) . bits ( ) ;
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return read_lvl;
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}
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}
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}
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- /// Recevies one radio packet and copies its contents into the given `packet` buffer
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+ /// Receives one radio packet and copies its contents into the given `packet` buffer
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///
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/// This methods returns the `Ok` variant if the CRC included the packet was successfully
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/// validated by the hardware; otherwise it returns the `Err` variant. In either case, `packet`
@@ -645,9 +645,7 @@ impl<'c> Radio<'c> {
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fn wait_for_event ( & self , event : Event ) {
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match event {
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Event :: End => {
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- while self . radio . events_end . read ( ) . events_end ( ) . bit_is_clear ( ) {
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- continue ;
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- }
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+ while self . radio . events_end . read ( ) . events_end ( ) . bit_is_clear ( ) { }
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self . radio . events_end . reset ( ) ;
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}
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Event :: PhyEnd => {
@@ -657,19 +655,15 @@ impl<'c> Radio<'c> {
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. read ( )
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. events_phyend ( )
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. bit_is_clear ( )
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- {
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- continue ;
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- }
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+ { }
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self . radio . events_phyend . reset ( ) ;
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}
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}
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}
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/// Waits until the radio state matches the given `state`
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fn wait_for_state_a ( & self , state : STATE_A ) {
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- while self . radio . state . read ( ) . state ( ) != state {
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- continue ;
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- }
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+ while self . radio . state . read ( ) . state ( ) != state { }
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}
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}
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