diff --git a/.travis.yml b/.travis.yml index a6648e2e..54d6dd3a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,5 +5,6 @@ rust: - nightly install: - rustup target add thumbv7em-none-eabi thumbv7em-none-eabihf thumbv8m.main-none-eabi + - rustup component add rustfmt script: - scripts/build.sh diff --git a/boards/actinius-icarus/examples/blinky.rs b/boards/actinius-icarus/examples/blinky.rs old mode 100755 new mode 100644 diff --git a/boards/actinius-icarus/src/lib.rs b/boards/actinius-icarus/src/lib.rs old mode 100755 new mode 100644 index 20862d4b..d30a7f46 --- a/boards/actinius-icarus/src/lib.rs +++ b/boards/actinius-icarus/src/lib.rs @@ -21,7 +21,7 @@ use hal::{ uarte::{self, Baudrate as UartBaudrate, Parity as UartParity, Uarte}, }; -use hal::prelude::{OutputPin, InputPin}; +use hal::prelude::{InputPin, OutputPin}; pub use hal::pac; diff --git a/boards/adafruit-nrf52-bluefruit-le/examples/blinky.rs b/boards/adafruit-nrf52-bluefruit-le/examples/blinky.rs index 0384ecff..1a43b525 100644 --- a/boards/adafruit-nrf52-bluefruit-le/examples/blinky.rs +++ b/boards/adafruit-nrf52-bluefruit-le/examples/blinky.rs @@ -1,17 +1,14 @@ #![no_main] #![no_std] - extern crate panic_halt; - use adafruit_nrf52_bluefruit_le::{prelude::*, Board}; use core::fmt::Write; use cortex_m_rt::{entry, exception, ExceptionFrame}; use nb::block; use nrf52832_hal::timer::{self, Timer}; - #[entry] fn main() -> ! { let mut b = Board::take().unwrap(); diff --git a/boards/adafruit_nrf52pro/examples/blinky.rs b/boards/adafruit_nrf52pro/examples/blinky.rs index 295a3dad..5a8bbdae 100644 --- a/boards/adafruit_nrf52pro/examples/blinky.rs +++ b/boards/adafruit_nrf52pro/examples/blinky.rs @@ -8,11 +8,11 @@ use nb::block; use panic_semihosting; use adafruit_nrf52pro_bsc::hal::{ - prelude::*, gpio::{p0, Level}, + prelude::*, timer::{self, Timer}, }; -use adafruit_nrf52pro_bsc::nrf52832_pac::{Peripherals}; +use adafruit_nrf52pro_bsc::nrf52832_pac::Peripherals; use adafruit_nrf52pro_bsc::Pins; #[entry] diff --git a/boards/adafruit_nrf52pro/src/lib.rs b/boards/adafruit_nrf52pro/src/lib.rs index e38b2c05..d07224a8 100644 --- a/boards/adafruit_nrf52pro/src/lib.rs +++ b/boards/adafruit_nrf52pro/src/lib.rs @@ -1,7 +1,7 @@ #![no_std] -pub use nrf52832_hal as hal; use crate::hal::gpio::{p0, Floating, Input}; pub use crate::hal::nrf52832_pac; +pub use nrf52832_hal as hal; /// Maps the pins to the names printed on the device pub struct Pins { diff --git a/boards/nRF52-DK/examples/blinky.rs b/boards/nRF52-DK/examples/blinky.rs index 182bbdb8..7da50f11 100644 --- a/boards/nRF52-DK/examples/blinky.rs +++ b/boards/nRF52-DK/examples/blinky.rs @@ -2,13 +2,13 @@ #![no_main] extern crate cortex_m_rt as rt; -extern crate panic_semihosting; -extern crate nrf52_dk_bsp as dk; extern crate nb; +extern crate nrf52_dk_bsp as dk; +extern crate panic_semihosting; -use dk::{ Board, prelude::*, nrf52832_hal::Timer }; -use rt::entry; +use dk::{nrf52832_hal::Timer, prelude::*, Board}; use nb::block; +use rt::entry; #[entry] fn main() -> ! { diff --git a/boards/nRF52-DK/src/lib.rs b/boards/nRF52-DK/src/lib.rs index 6a3e19cd..d176da86 100644 --- a/boards/nRF52-DK/src/lib.rs +++ b/boards/nRF52-DK/src/lib.rs @@ -14,27 +14,9 @@ pub mod prelude { } use nrf52832_hal::{ - gpio::{ - p0, - Pin, - Floating, - Input, - Output, - PushPull, - PullUp, - Level, - }, - nrf52832_pac::{ - self as nrf52, - CorePeripherals, - Peripherals, - }, - uarte::{ - self, - Uarte, - Parity as UartParity, - Baudrate as UartBaudrate, - }, + gpio::{p0, Floating, Input, Level, Output, Pin, PullUp, PushPull}, + nrf52832_pac::{self as nrf52, CorePeripherals, Peripherals}, + uarte::{self, Baudrate as UartBaudrate, Parity as UartParity, Uarte}, }; use nrf52832_hal::prelude::OutputPin; @@ -270,10 +252,7 @@ impl Board { /// This method will return an instance of `nRF52DK` the first time it is /// called. It will return only `None` on subsequent calls. pub fn take() -> Option { - Some(Self::new( - CorePeripherals::take()?, - Peripherals::take()?, - )) + Some(Self::new(CorePeripherals::take()?, Peripherals::take()?)) } /// Steal the peripherals @@ -289,10 +268,7 @@ impl Board { /// /// Always use `nRF52DK::take`, unless you really know what you're doing. pub unsafe fn steal() -> Self { - Self::new( - CorePeripherals::steal(), - Peripherals::steal(), - ) + Self::new(CorePeripherals::steal(), Peripherals::steal()) } fn new(cp: CorePeripherals, p: Peripherals) -> Self { @@ -302,15 +278,15 @@ impl Board { // It features HWFC but does not have to use it. // It can transmit a flexible baudrate of up to 1Mbps. let cdc_uart = Uarte::new( - p.UARTE0, - uarte::Pins { + p.UARTE0, + uarte::Pins { txd: pins0.p0_06.into_push_pull_output(Level::High).degrade(), rxd: pins0.p0_08.into_floating_input().degrade(), cts: Some(pins0.p0_07.into_floating_input().degrade()), rts: Some(pins0.p0_05.into_push_pull_output(Level::High).degrade()), }, UartParity::EXCLUDED, - UartBaudrate::BAUD115200 + UartBaudrate::BAUD115200, ); Board { @@ -318,22 +294,22 @@ impl Board { pins: Pins { _RESET: pins0.p0_21, - P0_02 : pins0.p0_02, - P0_03 : pins0.p0_03, - P0_04 : pins0.p0_04, - P0_11 : pins0.p0_11, - P0_12 : pins0.p0_12, - P0_24 : pins0.p0_24, - P0_25 : pins0.p0_25, - P0_28 : pins0.p0_28, - P0_29 : pins0.p0_29, - P0_30 : pins0.p0_30, - P0_31 : pins0.p0_31, - - P0_22 : pins0.p0_22, - P0_23 : pins0.p0_23, - P0_26 : pins0.p0_26, - P0_27 : pins0.p0_27, + P0_02: pins0.p0_02, + P0_03: pins0.p0_03, + P0_04: pins0.p0_04, + P0_11: pins0.p0_11, + P0_12: pins0.p0_12, + P0_24: pins0.p0_24, + P0_25: pins0.p0_25, + P0_28: pins0.p0_28, + P0_29: pins0.p0_29, + P0_30: pins0.p0_30, + P0_31: pins0.p0_31, + + P0_22: pins0.p0_22, + P0_23: pins0.p0_23, + P0_26: pins0.p0_26, + P0_27: pins0.p0_27, }, leds: Leds { @@ -356,87 +332,86 @@ impl Board { }, // Core peripherals - CBP : cp.CBP, + CBP: cp.CBP, CPUID: cp.CPUID, - DCB : cp.DCB, - DWT : cp.DWT, - FPB : cp.FPB, - FPU : cp.FPU, - ITM : cp.ITM, - MPU : cp.MPU, - NVIC : cp.NVIC, - SCB : cp.SCB, - SYST : cp.SYST, - TPIU : cp.TPIU, + DCB: cp.DCB, + DWT: cp.DWT, + FPB: cp.FPB, + FPU: cp.FPU, + ITM: cp.ITM, + MPU: cp.MPU, + NVIC: cp.NVIC, + SCB: cp.SCB, + SYST: cp.SYST, + TPIU: cp.TPIU, // nRF52 peripherals - FICR : p.FICR, - UICR : p.UICR, - POWER : p.POWER, - CLOCK : p.CLOCK, - RADIO : p.RADIO, - - UART0 : p.UART0, - SPIM0 : p.SPIM0, - SPIS0 : p.SPIS0, - TWIM0 : p.TWIM0, - TWIS0 : p.TWIS0, - SPI0 : p.SPI0, - TWI0 : p.TWI0, - SPIM1 : p.SPIM1, - SPIS1 : p.SPIS1, - TWIS1 : p.TWIS1, - SPI1 : p.SPI1, - TWI1 : p.TWI1, - NFCT : p.NFCT, + FICR: p.FICR, + UICR: p.UICR, + POWER: p.POWER, + CLOCK: p.CLOCK, + RADIO: p.RADIO, + + UART0: p.UART0, + SPIM0: p.SPIM0, + SPIS0: p.SPIS0, + TWIM0: p.TWIM0, + TWIS0: p.TWIS0, + SPI0: p.SPI0, + TWI0: p.TWI0, + SPIM1: p.SPIM1, + SPIS1: p.SPIS1, + TWIS1: p.TWIS1, + SPI1: p.SPI1, + TWI1: p.TWI1, + NFCT: p.NFCT, GPIOTE: p.GPIOTE, - SAADC : p.SAADC, + SAADC: p.SAADC, TIMER0: p.TIMER0, TIMER1: p.TIMER1, TIMER2: p.TIMER2, - RTC0 : p.RTC0, - TEMP : p.TEMP, - RNG : p.RNG, - ECB : p.ECB, - CCM : p.CCM, - AAR : p.AAR, - WDT : p.WDT, - RTC1 : p.RTC1, - QDEC : p.QDEC, - COMP : p.COMP, + RTC0: p.RTC0, + TEMP: p.TEMP, + RNG: p.RNG, + ECB: p.ECB, + CCM: p.CCM, + AAR: p.AAR, + WDT: p.WDT, + RTC1: p.RTC1, + QDEC: p.QDEC, + COMP: p.COMP, LPCOMP: p.LPCOMP, - SWI0 : p.SWI0, - EGU0 : p.EGU0, - SWI1 : p.SWI1, - EGU1 : p.EGU1, - SWI2 : p.SWI2, - EGU2 : p.EGU2, - SWI3 : p.SWI3, - EGU3 : p.EGU3, - SWI4 : p.SWI4, - EGU4 : p.EGU4, - SWI5 : p.SWI5, - EGU5 : p.EGU5, + SWI0: p.SWI0, + EGU0: p.EGU0, + SWI1: p.SWI1, + EGU1: p.EGU1, + SWI2: p.SWI2, + EGU2: p.EGU2, + SWI3: p.SWI3, + EGU3: p.EGU3, + SWI4: p.SWI4, + EGU4: p.EGU4, + SWI5: p.SWI5, + EGU5: p.EGU5, TIMER3: p.TIMER3, TIMER4: p.TIMER4, - PWM0 : p.PWM0, - PDM : p.PDM, - NVMC : p.NVMC, - PPI : p.PPI, - MWU : p.MWU, - PWM1 : p.PWM1, - PWM2 : p.PWM2, - RTC2 : p.RTC2, - I2S : p.I2S, + PWM0: p.PWM0, + PDM: p.PDM, + NVMC: p.NVMC, + PPI: p.PPI, + MWU: p.MWU, + PWM1: p.PWM1, + PWM2: p.PWM2, + RTC2: p.RTC2, + I2S: p.I2S, } } } - /// The nRF52 pins that are available on the nRF52DK #[allow(non_snake_case)] pub struct Pins { - _RESET : p0::P0_21>, + _RESET: p0::P0_21>, pub P0_03: p0::P0_03>, pub P0_04: p0::P0_04>, @@ -458,7 +433,6 @@ pub struct Pins { pub P0_27: p0::P0_27>, } - /// The LEDs on the nRF52-DK board pub struct Leds { /// nRF52-DK: LED1, nRF52: P0.17 diff --git a/boards/nRF52840-DK/examples/blinky.rs b/boards/nRF52840-DK/examples/blinky.rs index 671fe5b9..28f4f4c6 100644 --- a/boards/nRF52840-DK/examples/blinky.rs +++ b/boards/nRF52840-DK/examples/blinky.rs @@ -15,7 +15,6 @@ use nrf52840_dk_bsp::{ Board, }; - #[entry] fn main() -> ! { let mut nrf52 = Board::take().unwrap(); diff --git a/boards/nRF52840-DK/src/lib.rs b/boards/nRF52840-DK/src/lib.rs index 51db4da0..4d4d961b 100644 --- a/boards/nRF52840-DK/src/lib.rs +++ b/boards/nRF52840-DK/src/lib.rs @@ -18,34 +18,10 @@ pub mod prelude { // pub mod debug; use nrf52840_hal::{ - gpio::{ - p0, - p1, - Pin, - Floating, - Input, - Output, - PushPull, - PullUp, - Level, - }, - nrf52840_pac::{ - self as nrf52, - CorePeripherals, - Peripherals, - }, - spim::{ - self, - Frequency, - MODE_0, - Spim - }, - uarte::{ - self, - Uarte, - Parity as UartParity, - Baudrate as UartBaudrate, - }, + gpio::{p0, p1, Floating, Input, Level, Output, Pin, PullUp, PushPull}, + nrf52840_pac::{self as nrf52, CorePeripherals, Peripherals}, + spim::{self, Frequency, Spim, MODE_0}, + uarte::{self, Baudrate as UartBaudrate, Parity as UartParity, Uarte}, }; use embedded_hal::digital::v2::OutputPin; @@ -288,10 +264,7 @@ impl Board { /// This method will return an instance of `nRF52840DK` the first time it is /// called. It will return only `None` on subsequent calls. pub fn take() -> Option { - Some(Self::new( - CorePeripherals::take()?, - Peripherals::take()?, - )) + Some(Self::new(CorePeripherals::take()?, Peripherals::take()?)) } /// Steal the peripherals @@ -307,10 +280,7 @@ impl Board { /// /// Always use `nRF52840DK::take`, unless you really know what you're doing. pub unsafe fn steal() -> Self { - Self::new( - CorePeripherals::steal(), - Peripherals::steal(), - ) + Self::new(CorePeripherals::steal(), Peripherals::steal()) } fn new(cp: CorePeripherals, p: Peripherals) -> Self { @@ -319,11 +289,17 @@ impl Board { // The nRF52840-DK has an 64MB SPI flash on board which can be interfaced through SPI or Quad SPI. // As for now, only the normal SPI mode is available, so we are using this for the interface. - let flash_spim = Spim::new(p.SPIM2, spim::Pins { - sck : pins0.p0_19.into_push_pull_output(Level::Low).degrade(), - mosi: Some(pins0.p0_20.into_push_pull_output(Level::Low).degrade()), - miso: Some(pins0.p0_21.into_floating_input().degrade()), - }, Frequency::K500, MODE_0, 0); + let flash_spim = Spim::new( + p.SPIM2, + spim::Pins { + sck: pins0.p0_19.into_push_pull_output(Level::Low).degrade(), + mosi: Some(pins0.p0_20.into_push_pull_output(Level::Low).degrade()), + miso: Some(pins0.p0_21.into_floating_input().degrade()), + }, + Frequency::K500, + MODE_0, + 0, + ); let flash_cs = pins0.p0_17.into_push_pull_output(Level::High).degrade(); @@ -339,7 +315,7 @@ impl Board { rts: Some(pins0.p0_05.into_push_pull_output(Level::High).degrade()), }, UartParity::EXCLUDED, - UartBaudrate::BAUD115200 + UartBaudrate::BAUD115200, ); Board { @@ -348,33 +324,33 @@ impl Board { flash_cs: flash_cs, pins: Pins { - P0_03 : pins0.p0_03, - P0_04 : pins0.p0_04, - _RESET : pins0.p0_18, - P0_22 : pins0.p0_22, - P0_23 : pins0.p0_23, - P0_26 : pins0.p0_26, - P0_27 : pins0.p0_27, - P0_28 : pins0.p0_28, - P0_29 : pins0.p0_29, - P0_30 : pins0.p0_30, - P0_31 : pins0.p0_31, - P1_00 : pins1.p1_00, - P1_01 : pins1.p1_01, - P1_02 : pins1.p1_02, - P1_03 : pins1.p1_03, - P1_04 : pins1.p1_04, - P1_05 : pins1.p1_05, - P1_06 : pins1.p1_06, - P1_07 : pins1.p1_07, - P1_08 : pins1.p1_08, - P1_09 : pins1.p1_09, - P1_10 : pins1.p1_10, - P1_11 : pins1.p1_11, - P1_12 : pins1.p1_12, - P1_13 : pins1.p1_13, - P1_14 : pins1.p1_14, - P1_15 : pins1.p1_15, + P0_03: pins0.p0_03, + P0_04: pins0.p0_04, + _RESET: pins0.p0_18, + P0_22: pins0.p0_22, + P0_23: pins0.p0_23, + P0_26: pins0.p0_26, + P0_27: pins0.p0_27, + P0_28: pins0.p0_28, + P0_29: pins0.p0_29, + P0_30: pins0.p0_30, + P0_31: pins0.p0_31, + P1_00: pins1.p1_00, + P1_01: pins1.p1_01, + P1_02: pins1.p1_02, + P1_03: pins1.p1_03, + P1_04: pins1.p1_04, + P1_05: pins1.p1_05, + P1_06: pins1.p1_06, + P1_07: pins1.p1_07, + P1_08: pins1.p1_08, + P1_09: pins1.p1_09, + P1_10: pins1.p1_10, + P1_11: pins1.p1_11, + P1_12: pins1.p1_12, + P1_13: pins1.p1_13, + P1_14: pins1.p1_14, + P1_15: pins1.p1_15, }, leds: Leds { @@ -397,90 +373,89 @@ impl Board { }, // Core peripherals - CBP : cp.CBP, + CBP: cp.CBP, CPUID: cp.CPUID, - DCB : cp.DCB, - DWT : cp.DWT, - FPB : cp.FPB, - FPU : cp.FPU, - ITM : cp.ITM, - MPU : cp.MPU, - NVIC : cp.NVIC, - SCB : cp.SCB, - SYST : cp.SYST, - TPIU : cp.TPIU, + DCB: cp.DCB, + DWT: cp.DWT, + FPB: cp.FPB, + FPU: cp.FPU, + ITM: cp.ITM, + MPU: cp.MPU, + NVIC: cp.NVIC, + SCB: cp.SCB, + SYST: cp.SYST, + TPIU: cp.TPIU, // nRF52 peripherals - FICR : p.FICR, - UICR : p.UICR, - ACL : p.ACL, - POWER : p.POWER, - CLOCK : p.CLOCK, - RADIO : p.RADIO, - - UART0 : p.UART0, - SPIM0 : p.SPIM0, - SPIS0 : p.SPIS0, - TWIM0 : p.TWIM0, - TWIS0 : p.TWIS0, - SPI0 : p.SPI0, - TWI0 : p.TWI0, - SPIM1 : p.SPIM1, - SPIS1 : p.SPIS1, - TWIS1 : p.TWIS1, - SPI1 : p.SPI1, - TWI1 : p.TWI1, - NFCT : p.NFCT, + FICR: p.FICR, + UICR: p.UICR, + ACL: p.ACL, + POWER: p.POWER, + CLOCK: p.CLOCK, + RADIO: p.RADIO, + + UART0: p.UART0, + SPIM0: p.SPIM0, + SPIS0: p.SPIS0, + TWIM0: p.TWIM0, + TWIS0: p.TWIS0, + SPI0: p.SPI0, + TWI0: p.TWI0, + SPIM1: p.SPIM1, + SPIS1: p.SPIS1, + TWIS1: p.TWIS1, + SPI1: p.SPI1, + TWI1: p.TWI1, + NFCT: p.NFCT, GPIOTE: p.GPIOTE, - SAADC : p.SAADC, + SAADC: p.SAADC, TIMER0: p.TIMER0, TIMER1: p.TIMER1, TIMER2: p.TIMER2, - RTC0 : p.RTC0, - TEMP : p.TEMP, - RNG : p.RNG, - ECB : p.ECB, - CCM : p.CCM, - AAR : p.AAR, - WDT : p.WDT, - RTC1 : p.RTC1, - QDEC : p.QDEC, - COMP : p.COMP, + RTC0: p.RTC0, + TEMP: p.TEMP, + RNG: p.RNG, + ECB: p.ECB, + CCM: p.CCM, + AAR: p.AAR, + WDT: p.WDT, + RTC1: p.RTC1, + QDEC: p.QDEC, + COMP: p.COMP, LPCOMP: p.LPCOMP, - SWI0 : p.SWI0, - EGU0 : p.EGU0, - SWI1 : p.SWI1, - EGU1 : p.EGU1, - SWI2 : p.SWI2, - EGU2 : p.EGU2, - SWI3 : p.SWI3, - EGU3 : p.EGU3, - SWI4 : p.SWI4, - EGU4 : p.EGU4, - SWI5 : p.SWI5, - EGU5 : p.EGU5, + SWI0: p.SWI0, + EGU0: p.EGU0, + SWI1: p.SWI1, + EGU1: p.EGU1, + SWI2: p.SWI2, + EGU2: p.EGU2, + SWI3: p.SWI3, + EGU3: p.EGU3, + SWI4: p.SWI4, + EGU4: p.EGU4, + SWI5: p.SWI5, + EGU5: p.EGU5, TIMER3: p.TIMER3, TIMER4: p.TIMER4, - PWM0 : p.PWM0, - PDM : p.PDM, - NVMC : p.NVMC, - PPI : p.PPI, - MWU : p.MWU, - PWM1 : p.PWM1, - PWM2 : p.PWM2, - RTC2 : p.RTC2, - I2S : p.I2S, + PWM0: p.PWM0, + PDM: p.PDM, + NVMC: p.NVMC, + PPI: p.PPI, + MWU: p.MWU, + PWM1: p.PWM1, + PWM2: p.PWM2, + RTC2: p.RTC2, + I2S: p.I2S, } } } - /// The nRF52 pins that are available on the nRF52840DK #[allow(non_snake_case)] pub struct Pins { pub P0_03: p0::P0_03>, pub P0_04: p0::P0_04>, - _RESET: p0::P0_18>, + _RESET: p0::P0_18>, pub P0_22: p0::P0_22>, pub P0_23: p0::P0_23>, pub P0_26: p0::P0_26>, @@ -507,7 +482,6 @@ pub struct Pins { pub P1_15: p1::P1_15>, } - /// The LEDs on the nRF52840-DK board pub struct Leds { /// nRF52840-DK: LED1, nRF52: P0.30 diff --git a/boards/nRF9160-DK/examples/blinky.rs b/boards/nRF9160-DK/examples/blinky.rs index 84a5bac6..e6bedd7e 100644 --- a/boards/nRF9160-DK/examples/blinky.rs +++ b/boards/nRF9160-DK/examples/blinky.rs @@ -6,8 +6,8 @@ extern crate nb; extern crate nrf9160_dk_bsp as bsp; extern crate panic_semihosting; -use core::fmt::Write; use bsp::{hal::Timer, prelude::*, Board}; +use core::fmt::Write; use nb::block; use rt::entry; diff --git a/boards/nRF9160-DK/src/lib.rs b/boards/nRF9160-DK/src/lib.rs index a463e7b1..940870e3 100644 --- a/boards/nRF9160-DK/src/lib.rs +++ b/boards/nRF9160-DK/src/lib.rs @@ -19,7 +19,7 @@ use hal::{ uarte::{self, Baudrate as UartBaudrate, Parity as UartParity, Uarte}, }; -use hal::prelude::{OutputPin, InputPin}; +use hal::prelude::{InputPin, OutputPin}; pub use hal::pac; diff --git a/examples/rtfm-demo/src/main.rs b/examples/rtfm-demo/src/main.rs index 6bc7ca63..46164d47 100644 --- a/examples/rtfm-demo/src/main.rs +++ b/examples/rtfm-demo/src/main.rs @@ -16,7 +16,6 @@ use nrf52832_hal as hal; #[cfg(feature = "52840")] use nrf52840_hal as hal; - #[app(device = crate::hal::target)] const APP: () = { #[init] diff --git a/examples/twi-ssd1306/src/main.rs b/examples/twi-ssd1306/src/main.rs index 2491b37e..1f113c2b 100644 --- a/examples/twi-ssd1306/src/main.rs +++ b/examples/twi-ssd1306/src/main.rs @@ -12,19 +12,18 @@ use ssd1306::Builder; #[cfg(feature = "52832")] use nrf52832_hal::{ - nrf52832_pac as pac, gpio::*, + nrf52832_pac as pac, twim::{self, Twim}, }; #[cfg(feature = "52840")] use nrf52840_hal::{ - nrf52840_pac as pac, gpio::*, + nrf52840_pac as pac, twim::{self, Twim}, }; - /// TWI write example code using an SSD1306 OLED display: /// https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf /// diff --git a/nrf52-hal-common/src/clocks.rs b/nrf52-hal-common/src/clocks.rs index b33f372e..cb132d14 100644 --- a/nrf52-hal-common/src/clocks.rs +++ b/nrf52-hal-common/src/clocks.rs @@ -1,10 +1,10 @@ //! Configuration and control of the High and Low Frequency Clock //! sources -#[cfg(feature="9160")] +#[cfg(feature = "9160")] use crate::target::CLOCK_NS as CLOCK; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] use crate::target::CLOCK; // ZST Type States diff --git a/nrf52-hal-common/src/delay.rs b/nrf52-hal-common/src/delay.rs index 8d2564ba..391888ee 100644 --- a/nrf52-hal-common/src/delay.rs +++ b/nrf52-hal-common/src/delay.rs @@ -1,10 +1,10 @@ //! Delays use cast::u32; -use cortex_m::peripheral::SYST; use cortex_m::peripheral::syst::SystClkSource; +use cortex_m::peripheral::SYST; -use crate::hal::blocking::delay::{DelayMs, DelayUs}; use crate::clocks::HFCLK_FREQ; +use crate::hal::blocking::delay::{DelayMs, DelayUs}; /// System timer (SysTick) as a delay provider pub struct Delay { @@ -46,7 +46,7 @@ impl DelayMs for Delay { impl DelayUs for Delay { fn delay_us(&mut self, us: u32) { // The SysTick Reload Value register supports values between 1 and 0x00FFFFFF. - const MAX_RVR: u32 = 0x00FF_FFFF; + const MAX_RVR: u32 = 0x00FF_FFFF; let mut total_rvr = us * (HFCLK_FREQ / 1_000_000); diff --git a/nrf52-hal-common/src/gpio.rs b/nrf52-hal-common/src/gpio.rs index b8739400..477860dd 100644 --- a/nrf52-hal-common/src/gpio.rs +++ b/nrf52-hal-common/src/gpio.rs @@ -21,7 +21,6 @@ pub struct Output { _mode: PhantomData, } - /// Push pull output (type state) pub struct PushPull; /// Open drain output (type state) @@ -32,14 +31,12 @@ pub struct OpenDrain; // _mode: PhantomData, // } - /// Represents a digital input or output level pub enum Level { Low, High, } - // =============================================================== // Implement Generic Pins for this port, which allows you to use // other peripherals without having to be completely rust-generic @@ -53,16 +50,16 @@ pub struct Pin { _mode: PhantomData, } -#[cfg(feature="9160")] +#[cfg(feature = "9160")] use crate::target::P0_NS as P0; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] use crate::target::P0; #[cfg(feature = "52840")] -use crate::target::{ P1 }; +use crate::target::P1; -use crate::hal::digital::v2::{OutputPin, StatefulOutputPin, InputPin}; +use crate::hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin}; use void::Void; impl Pin { @@ -71,105 +68,143 @@ impl Pin { unsafe { &(*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).pin_cnf[self.pin as usize] + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .pin_cnf[self.pin as usize] } .write(|w| { - w.dir().input() - .input().connect() - .pull().disabled() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().disabled(); + w.drive().s0s1(); + w.sense().disabled(); + w }); Pin { _mode: PhantomData, #[cfg(feature = "52840")] port: self.port, - pin: self.pin + pin: self.pin, } } pub fn into_pullup_input(self) -> Pin> { unsafe { &(*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).pin_cnf[self.pin as usize] + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .pin_cnf[self.pin as usize] } .write(|w| { - w.dir().input() - .input().connect() - .pull().pullup() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().pullup(); + w.drive().s0s1(); + w.sense().disabled(); + w }); Pin { _mode: PhantomData, #[cfg(feature = "52840")] port: self.port, - pin: self.pin + pin: self.pin, } } pub fn into_pulldown_input(self) -> Pin> { unsafe { &(*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).pin_cnf[self.pin as usize] + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .pin_cnf[self.pin as usize] } .write(|w| { - w.dir().input() - .input().connect() - .pull().pulldown() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().pulldown(); + w.drive().s0s1(); + w.sense().disabled(); + w }); Pin { _mode: PhantomData, #[cfg(feature = "52840")] port: self.port, - pin: self.pin + pin: self.pin, } } /// Convert the pin to be a push-pull output with normal drive - pub fn into_push_pull_output(self, initial_output: Level) - -> Pin> - { + pub fn into_push_pull_output(self, initial_output: Level) -> Pin> { let mut pin = Pin { _mode: PhantomData, #[cfg(feature = "52840")] port: self.port, - pin: self.pin + pin: self.pin, }; match initial_output { - Level::Low => pin.set_low().unwrap(), + Level::Low => pin.set_low().unwrap(), Level::High => pin.set_high().unwrap(), } unsafe { &(*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).pin_cnf[self.pin as usize] + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .pin_cnf[self.pin as usize] } .write(|w| { - w.dir().output() - .input().connect() // AJM - hack for SPI - .pull().disabled() - .drive().s0s1() - .sense().disabled() + w.dir().output(); + w.input().connect(); // AJM - hack for SPI + w.pull().disabled(); + w.drive().s0s1(); + w.sense().disabled(); + w }); pin @@ -179,21 +214,20 @@ impl Pin { /// /// This method currently does not support configuring an /// internal pull-up or pull-down resistor. - pub fn into_open_drain_output(self, - config: OpenDrainConfig, + pub fn into_open_drain_output( + self, + config: OpenDrainConfig, initial_output: Level, - ) - -> Pin> - { + ) -> Pin> { let mut pin = Pin { _mode: PhantomData, #[cfg(feature = "52840")] port: self.port, - pin: self.pin + pin: self.pin, }; match initial_output { - Level::Low => pin.set_low().unwrap(), + Level::Low => pin.set_low().unwrap(), Level::High => pin.set_high().unwrap(), } @@ -202,18 +236,27 @@ impl Pin { let pin_cnf = unsafe { &(*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).pin_cnf[self.pin as usize] + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .pin_cnf[self.pin as usize] }; pin_cnf.write(|w| { + w.dir().output(); + w.input().disconnect(); + w.pull().disabled(); + w.drive().variant(config.variant()); + w.sense().disabled(); w - .dir().output() - .input().disconnect() - .pull().disabled() - .drive().variant(config.variant()) - .sense().disabled() }); pin @@ -228,14 +271,27 @@ impl InputPin for Pin> { } fn is_low(&self) -> Result { - Ok(unsafe { ( - (*{ + Ok(unsafe { + ((*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).in_.read().bits() & (1 << self.pin) - ) == 0 }) + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .in_ + .read() + .bits() + & (1 << self.pin)) + == 0 + }) } } @@ -249,10 +305,20 @@ impl OutputPin for Pin> { unsafe { (*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).outset.write(|w| w.bits(1u32 << self.pin)); + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .outset + .write(|w| w.bits(1u32 << self.pin)); } Ok(()) } @@ -264,10 +330,20 @@ impl OutputPin for Pin> { unsafe { (*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).outclr.write(|w| w.bits(1u32 << self.pin)); + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .outclr + .write(|w| w.bits(1u32 << self.pin)); } Ok(()) } @@ -283,14 +359,27 @@ impl StatefulOutputPin for Pin> { fn is_set_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects - TODO(AJM) verify? // TODO - I wish I could do something like `.pins$i()`... - Ok(unsafe { ( - (*{ + Ok(unsafe { + ((*{ #[cfg(not(feature = "52840"))] - { P0::ptr() } + { + P0::ptr() + } #[cfg(feature = "52840")] - { if !self.port { P0::ptr() } else { P1::ptr() } } - }).out.read().bits() & (1 << self.pin) - ) == 0 }) + { + if !self.port { + P0::ptr() + } else { + P1::ptr() + } + } + }) + .out + .read() + .bits() + & (1 << self.pin)) + == 0 + }) } } @@ -302,28 +391,20 @@ pub enum OpenDrainConfig { HighDrive0Disconnect1, } -#[cfg(feature="9160")] -use crate::target::p0_ns::{ - pin_cnf, - PIN_CNF, -}; - -#[cfg(not(feature="9160"))] -use crate::target::p0::{ - pin_cnf, - PIN_CNF, -}; - +#[cfg(feature = "9160")] +use crate::target::p0_ns::{pin_cnf, PIN_CNF}; +#[cfg(not(feature = "9160"))] +use crate::target::p0::{pin_cnf, PIN_CNF}; impl OpenDrainConfig { fn variant(self) -> pin_cnf::DRIVEW { use self::OpenDrainConfig::*; match self { - Disconnect0Standard1 => pin_cnf::DRIVEW::D0S1, + Disconnect0Standard1 => pin_cnf::DRIVEW::D0S1, Disconnect0HighDrive1 => pin_cnf::DRIVEW::D0H1, - Standard0Disconnect1 => pin_cnf::DRIVEW::S0D1, + Standard0Disconnect1 => pin_cnf::DRIVEW::S0D1, HighDrive0Disconnect1 => pin_cnf::DRIVEW::H0D1, } } @@ -399,11 +480,12 @@ macro_rules! gpio { /// Convert the pin to be a floating input pub fn into_floating_input(self) -> $PXi> { unsafe { &(*$PX::ptr()).pin_cnf[$i] }.write(|w| { - w.dir().input() - .input().connect() - .pull().disabled() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().disabled(); + w.drive().s0s1(); + w.sense().disabled(); + w }); $PXi { @@ -412,11 +494,12 @@ macro_rules! gpio { } pub fn into_pulldown_input(self) -> $PXi> { unsafe { &(*$PX::ptr()).pin_cnf[$i] }.write(|w| { - w.dir().input() - .input().connect() - .pull().pulldown() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().pulldown(); + w.drive().s0s1(); + w.sense().disabled(); + w }); $PXi { @@ -425,11 +508,12 @@ macro_rules! gpio { } pub fn into_pullup_input(self) -> $PXi> { unsafe { &(*$PX::ptr()).pin_cnf[$i] }.write(|w| { - w.dir().input() - .input().connect() - .pull().pullup() - .drive().s0s1() - .sense().disabled() + w.dir().input(); + w.input().connect(); + w.pull().pullup(); + w.drive().s0s1(); + w.sense().disabled(); + w }); $PXi { @@ -451,11 +535,12 @@ macro_rules! gpio { } unsafe { &(*$PX::ptr()).pin_cnf[$i] }.write(|w| { - w.dir().output() - .input().disconnect() - .pull().disabled() - .drive().s0s1() - .sense().disabled() + w.dir().output(); + w.input().disconnect(); + w.pull().disabled(); + w.drive().s0s1(); + w.sense().disabled(); + w }); pin @@ -486,12 +571,12 @@ macro_rules! gpio { &(*$PX::ptr()).pin_cnf[$i] }; pin_cnf.write(|w| { + w.dir().output(); + w.input().disconnect(); + w.pull().disabled(); + w.drive().variant(config.variant()); + w.sense().disabled(); w - .dir().output() - .input().disconnect() - .pull().disabled() - .drive().variant(config.variant()) - .sense().disabled() }); pin diff --git a/nrf52-hal-common/src/lib.rs b/nrf52-hal-common/src/lib.rs index 7601789e..27c8c18f 100644 --- a/nrf52-hal-common/src/lib.rs +++ b/nrf52-hal-common/src/lib.rs @@ -17,12 +17,12 @@ pub use nrf9160_pac as target; pub mod clocks; pub mod delay; pub mod gpio; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] pub mod rng; pub mod rtc; pub mod saadc; pub mod spim; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] pub mod temp; pub mod time; pub mod timer; @@ -30,8 +30,8 @@ pub mod twim; pub mod uarte; pub mod prelude { - pub use crate::hal::prelude::*; pub use crate::hal::digital::v2::*; + pub use crate::hal::prelude::*; pub use crate::time::U32Ext; } @@ -46,7 +46,7 @@ pub mod target_constants { pub const SRAM_UPPER: usize = 0x3000_0000; pub const FORCE_COPY_BUFFER_SIZE: usize = 255; } -#[cfg(any(feature = "52840", feature="9160"))] +#[cfg(any(feature = "52840", feature = "9160"))] pub mod target_constants { // NRF52840 and NRF9160 16 bits 1..0xFFFF pub const EASY_DMA_SIZE: usize = 65535; @@ -59,8 +59,7 @@ pub mod target_constants { /// Does this slice reside entirely within RAM? pub(crate) fn slice_in_ram(slice: &[u8]) -> bool { let ptr = slice.as_ptr() as usize; - ptr >= target_constants::SRAM_LOWER && - (ptr + slice.len()) < target_constants::SRAM_UPPER + ptr >= target_constants::SRAM_LOWER && (ptr + slice.len()) < target_constants::SRAM_UPPER } /// A handy structure for converting rust slices into ptr and len pairs @@ -73,10 +72,7 @@ pub(crate) struct DmaSlice { impl DmaSlice { pub fn null() -> Self { - Self { - ptr: 0, - len: 0, - } + Self { ptr: 0, len: 0 } } pub fn from_slice(slice: &[u8]) -> Self { @@ -89,7 +85,7 @@ impl DmaSlice { pub use crate::clocks::Clocks; pub use crate::delay::Delay; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] pub use crate::rng::Rng; pub use crate::rtc::Rtc; pub use crate::saadc::Saadc; diff --git a/nrf52-hal-common/src/rng.rs b/nrf52-hal-common/src/rng.rs index 2d863ddf..5acff95c 100644 --- a/nrf52-hal-common/src/rng.rs +++ b/nrf52-hal-common/src/rng.rs @@ -2,12 +2,10 @@ //! //! See nRF52832 product specification, chapter 26. - use rand_core::{CryptoRng, RngCore}; use crate::target::RNG; - /// Interface to the RNG peripheral /// /// Right now, this is very basic, only providing blocking interfaces. @@ -47,32 +45,28 @@ impl Rng { pub fn random_u16(&mut self) -> u16 { let mut buf = [0; 2]; self.random(&mut buf); - buf[0] as u16 | - (buf[1] as u16) << 8 + buf[0] as u16 | (buf[1] as u16) << 8 } /// Return a random `u32` pub fn random_u32(&mut self) -> u32 { let mut buf = [0; 4]; self.random(&mut buf); - buf[0] as u32 | - (buf[1] as u32) << 8 | - (buf[2] as u32) << 16 | - (buf[3] as u32) << 24 + buf[0] as u32 | (buf[1] as u32) << 8 | (buf[2] as u32) << 16 | (buf[3] as u32) << 24 } /// Return a random `u64` pub fn random_u64(&mut self) -> u64 { let mut buf = [0; 8]; self.random(&mut buf); - buf[0] as u64 | - (buf[1] as u64) << 8 | - (buf[2] as u64) << 16 | - (buf[3] as u64) << 24 | - (buf[4] as u64) << 32 | - (buf[5] as u64) << 40 | - (buf[6] as u64) << 48 | - (buf[7] as u64) << 56 + buf[0] as u64 + | (buf[1] as u64) << 8 + | (buf[2] as u64) << 16 + | (buf[3] as u64) << 24 + | (buf[4] as u64) << 32 + | (buf[5] as u64) << 40 + | (buf[6] as u64) << 48 + | (buf[7] as u64) << 56 } } diff --git a/nrf52-hal-common/src/rtc.rs b/nrf52-hal-common/src/rtc.rs index 10302c05..bad921c2 100644 --- a/nrf52-hal-common/src/rtc.rs +++ b/nrf52-hal-common/src/rtc.rs @@ -2,14 +2,13 @@ use core::ops::Deref; - -#[cfg(feature="9160")] +#[cfg(feature = "9160")] use crate::target::{rtc0_ns as rtc0, Interrupt, NVIC, RTC0_NS as RTC0, RTC1_NS as RTC1}; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] use crate::target::{rtc0, Interrupt, NVIC, RTC0, RTC1}; -#[cfg(any(feature = "52840", feature="52832"))] +#[cfg(any(feature = "52840", feature = "52832"))] use crate::target::RTC2; // Zero Size Type State structs @@ -235,7 +234,6 @@ where } } - /// Implemented by all RTC instances pub trait Instance: Deref { /// This interrupt associated with this RTC instance @@ -254,5 +252,5 @@ macro_rules! impl_instance { impl_instance!(RTC0, RTC1,); -#[cfg(any(feature = "52840", feature="52832"))] +#[cfg(any(feature = "52840", feature = "52832"))] impl_instance!(RTC2,); diff --git a/nrf52-hal-common/src/saadc.rs b/nrf52-hal-common/src/saadc.rs old mode 100755 new mode 100644 index 8989fa3e..b2ac687c --- a/nrf52-hal-common/src/saadc.rs +++ b/nrf52-hal-common/src/saadc.rs @@ -44,20 +44,14 @@ impl Saadc { saadc.samplerate.write(|w| w.mode().task()); saadc.ch[0].config.write(|w| { - w.refsel() - .variant(reference) - .gain() - .variant(gain) - .tacq() - .variant(time) - .mode() - .se() - .resp() - .variant(resistor) - .resn() - .bypass() - .burst() - .enabled() + w.refsel().variant(reference); + w.gain().variant(gain); + w.tacq().variant(time); + w.mode().se(); + w.resp().variant(resistor); + w.resn().bypass(); + w.burst().enabled(); + w }); saadc.ch[0].pseln.write(|w| w.pseln().nc()); diff --git a/nrf52-hal-common/src/spim.rs b/nrf52-hal-common/src/spim.rs index 61c5deb7..ca52a5a5 100644 --- a/nrf52-hal-common/src/spim.rs +++ b/nrf52-hal-common/src/spim.rs @@ -4,14 +4,14 @@ use core::ops::Deref; use core::sync::atomic::{compiler_fence, Ordering::SeqCst}; -#[cfg(feature="9160")] -use crate::target::{spim0_ns as spim0, SPIM0_NS as SPIM0 }; +#[cfg(feature = "9160")] +use crate::target::{spim0_ns as spim0, SPIM0_NS as SPIM0}; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] use crate::target::{spim0, SPIM0}; -pub use spim0::frequency::FREQUENCYW as Frequency; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; +pub use spim0::frequency::FREQUENCYW as Frequency; use core::iter::repeat_with; @@ -19,10 +19,9 @@ use core::iter::repeat_with; use crate::target::{SPIM1, SPIM2}; use crate::gpio::{Floating, Input, Output, Pin, PushPull}; -use embedded_hal::digital::v2::OutputPin; use crate::target_constants::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; use crate::{slice_in_ram, DmaSlice}; - +use embedded_hal::digital::v2::OutputPin; /// Interface to a SPIM instance /// @@ -43,10 +42,7 @@ where ram_slice_check(words)?; words.chunks(EASY_DMA_SIZE).try_for_each(|chunk| { - self.do_spi_dma_transfer( - DmaSlice::from_slice(chunk), - DmaSlice::from_slice(chunk), - ) + self.do_spi_dma_transfer(DmaSlice::from_slice(chunk), DmaSlice::from_slice(chunk)) })?; Ok(words) @@ -91,10 +87,7 @@ where let mut buf = [0u8; FORCE_COPY_BUFFER_SIZE]; buf[..chunk.len()].copy_from_slice(chunk); - self.do_spi_dma_transfer( - DmaSlice::from_slice(&buf[..chunk.len()]), - DmaSlice::null(), - ) + self.do_spi_dma_transfer(DmaSlice::from_slice(&buf[..chunk.len()]), DmaSlice::null()) } pub fn new(spim: T, pins: Pins, frequency: Frequency, mode: Mode, orc: u8) -> Self { @@ -132,14 +125,23 @@ where spim.config.write(|w| { // Can't match on `mode` due to embedded-hal, see https://github.com/rust-embedded/embedded-hal/pull/126 if mode == MODE_0 { - w.order().msb_first().cpol().active_high().cpha().leading() + w.order().msb_first(); + w.cpol().active_high(); + w.cpha().leading(); } else if mode == MODE_1 { - w.order().msb_first().cpol().active_high().cpha().trailing() + w.order().msb_first(); + w.cpol().active_high(); + w.cpha().trailing(); } else if mode == MODE_2 { - w.order().msb_first().cpol().active_low().cpha().leading() + w.order().msb_first(); + w.cpol().active_low(); + w.cpha().leading(); } else { - w.order().msb_first().cpol().active_low().cpha().trailing() + w.order().msb_first(); + w.cpol().active_low(); + w.cpha().trailing(); } + w }); // Configure frequency @@ -155,22 +157,14 @@ where } /// Internal helper function to setup and execute SPIM DMA transfer - fn do_spi_dma_transfer( - &mut self, - tx: DmaSlice, - rx: DmaSlice, - ) -> Result<(), Error> { - + fn do_spi_dma_transfer(&mut self, tx: DmaSlice, rx: DmaSlice) -> Result<(), Error> { // Conservative compiler fence to prevent optimizations that do not // take in to account actions by DMA. The fence has been placed here, // before any DMA action has started compiler_fence(SeqCst); // Set up the DMA write - self.0 - .txd - .ptr - .write(|w| unsafe { w.ptr().bits(tx.ptr) }); + self.0.txd.ptr.write(|w| unsafe { w.ptr().bits(tx.ptr) }); self.0.txd.maxcnt.write(|w| // Note that that nrf52840 maxcnt is a wider @@ -254,10 +248,7 @@ where // Don't return early, as we must reset the CS pin let res = buffer.chunks(EASY_DMA_SIZE).try_for_each(|chunk| { - self.do_spi_dma_transfer( - DmaSlice::from_slice(chunk), - DmaSlice::from_slice(chunk), - ) + self.do_spi_dma_transfer(DmaSlice::from_slice(chunk), DmaSlice::from_slice(chunk)) }); chip_select.set_high().unwrap(); @@ -341,7 +332,8 @@ where // back Nones, then we are done sending and receiving // // Don't return early, as we must reset the CS pin - let res = txi.zip(rxi) + let res = txi + .zip(rxi) .take_while(|(t, r)| t.is_some() && r.is_some()) // We also turn the slices into either a DmaSlice (if there was data), or a null // DmaSlice (if there is no data) @@ -353,9 +345,7 @@ where .unwrap_or_else(|| DmaSlice::null()), ) }) - .try_for_each(|(t, r)| { - self.do_spi_dma_transfer(t, r) - }); + .try_for_each(|(t, r)| self.do_spi_dma_transfer(t, r)); chip_select.set_high().unwrap(); @@ -414,7 +404,6 @@ fn ram_slice_check(slice: &[u8]) -> Result<(), Error> { } } - /// Implemented by all SPIM instances pub trait Instance: Deref {} diff --git a/nrf52-hal-common/src/temp.rs b/nrf52-hal-common/src/temp.rs index e54ed54a..f1c56ff4 100644 --- a/nrf52-hal-common/src/temp.rs +++ b/nrf52-hal-common/src/temp.rs @@ -1,9 +1,9 @@ //! Temperature sensor interface. +use crate::target::TEMP; use fpa::I30F2; use nb; use void::Void; -use crate::target::TEMP; /// Integrated temperature sensor. pub struct Temp(TEMP); diff --git a/nrf52-hal-common/src/timer.rs b/nrf52-hal-common/src/timer.rs index 7b39d68c..50b173d7 100644 --- a/nrf52-hal-common/src/timer.rs +++ b/nrf52-hal-common/src/timer.rs @@ -4,10 +4,13 @@ use core::ops::Deref; -#[cfg(feature="9160")] -use crate::target::{timer0_ns as timer0, Interrupt, NVIC, TIMER0_NS as TIMER0, TIMER1_NS as TIMER1, TIMER2_NS as TIMER2}; +#[cfg(feature = "9160")] +use crate::target::{ + timer0_ns as timer0, Interrupt, NVIC, TIMER0_NS as TIMER0, TIMER1_NS as TIMER1, + TIMER2_NS as TIMER2, +}; -#[cfg(not(feature="9160"))] +#[cfg(not(feature = "9160"))] use crate::target::{timer0, Interrupt, NVIC, TIMER0, TIMER1, TIMER2}; use embedded_hal::{prelude::*, timer}; @@ -22,7 +25,6 @@ use core::marker::PhantomData; pub struct OneShot; pub struct Periodic; - /// Interface to a TIMER instance /// /// Right now, this is a very basic interface. The timer will always be @@ -33,7 +35,7 @@ pub struct Periodic; pub struct Timer(T, PhantomData); impl Timer -where +where T: Instance, { pub fn one_shot(timer: T) -> Timer { @@ -51,7 +53,6 @@ where pub fn new(timer: T) -> Timer { Timer::::one_shot(timer) } - } impl Timer @@ -69,7 +70,6 @@ where Timer::(timer, PhantomData) } - } impl Timer @@ -227,11 +227,7 @@ where } } -impl timer::Periodic for Timer -where - T: Instance, -{} - +impl timer::Periodic for Timer where T: Instance {} /// Implemented by all `TIMER` instances pub trait Instance: Deref { diff --git a/nrf52-hal-common/src/twim.rs b/nrf52-hal-common/src/twim.rs index 205ca577..d46d1186 100644 --- a/nrf52-hal-common/src/twim.rs +++ b/nrf52-hal-common/src/twim.rs @@ -7,34 +7,21 @@ use core::ops::Deref; use core::sync::atomic::{compiler_fence, Ordering::SeqCst}; -#[cfg(feature="9160")] -use crate::target::{ - twim0_ns as twim0, - P0_NS as P0, - TWIM0_NS as TWIM0, -}; - -#[cfg(not(feature="9160"))] -use crate::target::{ - twim0, - P0, - TWIM0, -}; +#[cfg(feature = "9160")] +use crate::target::{twim0_ns as twim0, P0_NS as P0, TWIM0_NS as TWIM0}; + +#[cfg(not(feature = "9160"))] +use crate::target::{twim0, P0, TWIM0}; #[cfg(any(feature = "52832", feature = "52840"))] use crate::target::TWIM1; -use crate::gpio::{ - Pin, - Floating, - Input, -}; +use crate::gpio::{Floating, Input, Pin}; use crate::target_constants::EASY_DMA_SIZE; pub use twim0::frequency::FREQUENCYW as Frequency; - /// Interface to a TWIM instance /// /// This is a very basic interface that comes with the following limitation: @@ -46,7 +33,10 @@ pub use twim0::frequency::FREQUENCYW as Frequency; /// section 6.1.2 for nRF52840). pub struct Twim(T); -impl Twim where T: Instance { +impl Twim +where + T: Instance, +{ pub fn new(twim: T, pins: Pins, frequency: Frequency) -> Self { // The TWIM peripheral requires the pins to be in a mode that is not // exposed through the GPIO API, and might it might not make sense to @@ -57,14 +47,18 @@ impl Twim where T: Instance { // safe, as we own the pins now and have exclusive access to their // registers. for &pin in &[pins.scl.pin, pins.sda.pin] { - unsafe { &*P0::ptr() }.pin_cnf[pin as usize].write(|w| - w - .dir().input() - .input().connect() - .pull().pullup() - .drive().s0d1() - .sense().disabled() - ); + unsafe { &*P0::ptr() }.pin_cnf[pin as usize].write(|w| { + w.dir() + .input() + .input() + .connect() + .pull() + .pullup() + .drive() + .s0d1() + .sense() + .disabled() + }); } // Select pins @@ -82,14 +76,11 @@ impl Twim where T: Instance { }); // Enable TWIM instance - twim.enable.write(|w| - w.enable().enabled() - ); + twim.enable.write(|w| w.enable().enabled()); // Configure frequency twim.frequency.write(|w| w.frequency().variant(frequency)); - Twim(twim) } @@ -97,13 +88,7 @@ impl Twim where T: Instance { /// /// The buffer must have a length of at most 255 bytes on the nRF52832 /// and at most 65535 bytes on the nRF52840. - pub fn write(&mut self, - address: u8, - buffer: &[u8], - ) - -> Result<(), Error> - { - + pub fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> { if buffer.len() > EASY_DMA_SIZE { return Err(Error::TxBufferTooLong); } @@ -113,7 +98,9 @@ impl Twim where T: Instance { // before any DMA action has started compiler_fence(SeqCst); - self.0.address.write(|w| unsafe { w.address().bits(address) }); + self.0 + .address + .write(|w| unsafe { w.address().bits(address) }); // Set up the DMA write self.0.txd.ptr.write(|w| @@ -123,8 +110,7 @@ impl Twim where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(buffer.as_ptr() as u32) } - ); + unsafe { w.ptr().bits(buffer.as_ptr() as u32) }); self.0.txd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -132,14 +118,12 @@ impl Twim where T: Instance { // // The MAXCNT field is 8 bits wide and accepts the full range of // values. - unsafe { w.maxcnt().bits(buffer.len() as _) } - ); + unsafe { w.maxcnt().bits(buffer.len() as _) }); // Start write operation self.0.tasks_starttx.write(|w| // `1` is a valid value to write to task registers. - unsafe { w.bits(1) } - ); + unsafe { w.bits(1) }); // Wait until write operation is about to end while self.0.events_lasttx.read().bits() == 0 {} @@ -148,8 +132,7 @@ impl Twim where T: Instance { // Stop read operation self.0.tasks_stop.write(|w| // `1` is a valid value to write to task registers. - unsafe { w.bits(1) } - ); + unsafe { w.bits(1) }); // Wait until write operation has ended while self.0.events_stopped.read().bits() == 0 {} @@ -171,12 +154,7 @@ impl Twim where T: Instance { /// /// The buffer must have a length of at most 255 bytes on the nRF52832 /// and at most 65535 bytes on the nRF52840. - pub fn read(&mut self, - address: u8, - buffer: &mut [u8], - ) - -> Result<(), Error> - { + pub fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> { if buffer.len() > EASY_DMA_SIZE { return Err(Error::RxBufferTooLong); } @@ -186,7 +164,9 @@ impl Twim where T: Instance { // before any DMA action has started compiler_fence(SeqCst); - self.0.address.write(|w| unsafe { w.address().bits(address) }); + self.0 + .address + .write(|w| unsafe { w.address().bits(address) }); // Set up the DMA read self.0.rxd.ptr.write(|w| @@ -196,8 +176,7 @@ impl Twim where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(buffer.as_mut_ptr() as u32) } - ); + unsafe { w.ptr().bits(buffer.as_mut_ptr() as u32) }); self.0.rxd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -208,14 +187,12 @@ impl Twim where T: Instance { // type than a u8, so we use a `_` cast rather than a `u8` cast. // The MAXCNT field is thus at least 8 bits wide and accepts the // full range of values that fit in a `u8`. - unsafe { w.maxcnt().bits(buffer.len() as _) } - ); + unsafe { w.maxcnt().bits(buffer.len() as _) }); // Start read operation self.0.tasks_startrx.write(|w| // `1` is a valid value to write to task registers. - unsafe { w.bits(1) } - ); + unsafe { w.bits(1) }); // Wait until read operation is about to end while self.0.events_lastrx.read().bits() == 0 {} @@ -224,8 +201,7 @@ impl Twim where T: Instance { // Stop read operation self.0.tasks_stop.write(|w| // `1` is a valid value to write to task registers. - unsafe { w.bits(1) } - ); + unsafe { w.bits(1) }); // Wait until read operation has ended while self.0.events_stopped.read().bits() == 0 {} @@ -247,13 +223,12 @@ impl Twim where T: Instance { /// triggering a stop condition between the two /// /// The buffer must have a length of at most 255 bytes. - pub fn write_then_read(&mut self, + pub fn write_then_read( + &mut self, address: u8, - wr_buffer: &[u8], + wr_buffer: &[u8], rd_buffer: &mut [u8], - ) - -> Result<(), Error> - { + ) -> Result<(), Error> { if wr_buffer.len() > EASY_DMA_SIZE { return Err(Error::TxBufferTooLong); } @@ -267,7 +242,9 @@ impl Twim where T: Instance { // before any DMA action has started compiler_fence(SeqCst); - self.0.address.write(|w| unsafe { w.address().bits(address) }); + self.0 + .address + .write(|w| unsafe { w.address().bits(address) }); // Set up the DMA write self.0.txd.ptr.write(|w| @@ -277,8 +254,7 @@ impl Twim where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(wr_buffer.as_ptr() as u32) } - ); + unsafe { w.ptr().bits(wr_buffer.as_ptr() as u32) }); self.0.txd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -286,8 +262,7 @@ impl Twim where T: Instance { // // The MAXCNT field is 8 bits wide and accepts the full range of // values. - unsafe { w.maxcnt().bits(wr_buffer.len() as _) } - ); + unsafe { w.maxcnt().bits(wr_buffer.len() as _) }); // Set up the DMA read self.0.rxd.ptr.write(|w| @@ -297,8 +272,7 @@ impl Twim where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(rd_buffer.as_mut_ptr() as u32) } - ); + unsafe { w.ptr().bits(rd_buffer.as_mut_ptr() as u32) }); self.0.rxd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -309,20 +283,17 @@ impl Twim where T: Instance { // type than a u8, so we use a `_` cast rather than a `u8` cast. // The MAXCNT field is thus at least 8 bits wide and accepts the // full range of values that fit in a `u8`. - unsafe { w.maxcnt().bits(rd_buffer.len() as _) } - ); + unsafe { w.maxcnt().bits(rd_buffer.len() as _) }); // Immediately start RX after TX, then stop - self.0.shorts.modify(|_r, w| - w.lasttx_startrx().enabled() - .lastrx_stop().enabled() - ); + self.0 + .shorts + .modify(|_r, w| w.lasttx_startrx().enabled().lastrx_stop().enabled()); // Start write operation self.0.tasks_starttx.write(|w| // `1` is a valid value to write to task registers. - unsafe { w.bits(1) } - ); + unsafe { w.bits(1) }); // Wait until total operation has ended while self.0.events_stopped.read().bits() == 0 {} @@ -338,7 +309,7 @@ impl Twim where T: Instance { compiler_fence(SeqCst); let bad_write = self.0.txd.amount.read().bits() != wr_buffer.len() as u32; - let bad_read = self.0.rxd.amount.read().bits() != rd_buffer.len() as u32; + let bad_read = self.0.rxd.amount.read().bits() != rd_buffer.len() as u32; if bad_write { return Err(Error::Transmit); @@ -359,7 +330,10 @@ impl Twim where T: Instance { /// Implementation of embedded_hal::blocking::i2c Traits -impl embedded_hal::blocking::i2c::Write for Twim where T: Instance { +impl embedded_hal::blocking::i2c::Write for Twim +where + T: Instance, +{ type Error = Error; fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Error> { @@ -367,7 +341,10 @@ impl embedded_hal::blocking::i2c::Write for Twim where T: Instance { } } -impl embedded_hal::blocking::i2c::Read for Twim where T: Instance { +impl embedded_hal::blocking::i2c::Read for Twim +where + T: Instance, +{ type Error = Error; fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Error> { @@ -375,10 +352,18 @@ impl embedded_hal::blocking::i2c::Read for Twim where T: Instance { } } -impl embedded_hal::blocking::i2c::WriteRead for Twim where T: Instance { +impl embedded_hal::blocking::i2c::WriteRead for Twim +where + T: Instance, +{ type Error = Error; - fn write_read<'w>(&mut self, addr: u8, bytes:&'w[u8], buffer: &'w mut [u8]) -> Result<(), Error> { + fn write_read<'w>( + &mut self, + addr: u8, + bytes: &'w [u8], + buffer: &'w mut [u8], + ) -> Result<(), Error> { self.write_then_read(addr, bytes, buffer) } } @@ -394,7 +379,6 @@ pub struct Pins { pub sda: Pin>, } - #[derive(Debug)] pub enum Error { TxBufferTooLong, @@ -403,9 +387,8 @@ pub enum Error { Receive, } - /// Implemented by all TWIM instances -pub trait Instance: Deref {} +pub trait Instance: Deref {} impl Instance for TWIM0 {} diff --git a/nrf52-hal-common/src/uarte.rs b/nrf52-hal-common/src/uarte.rs index 280d7f25..8f46a2cb 100644 --- a/nrf52-hal-common/src/uarte.rs +++ b/nrf52-hal-common/src/uarte.rs @@ -4,45 +4,28 @@ //! //! - nrf52832: Section 35 //! - nrf52840: Section 6.34 +use core::fmt; use core::ops::Deref; use core::sync::atomic::{compiler_fence, Ordering::SeqCst}; -use core::fmt; use embedded_hal::digital::v2::OutputPin; -#[cfg(feature="52840")] +#[cfg(feature = "52840")] use crate::target::UARTE1; -#[cfg(feature="9160")] -use crate::target::{ - uarte0_ns as uarte0, - UARTE0_NS as UARTE0, - UARTE1_NS as UARTE1, -}; +#[cfg(feature = "9160")] +use crate::target::{uarte0_ns as uarte0, UARTE0_NS as UARTE0, UARTE1_NS as UARTE1}; -#[cfg(not(feature="9160"))] -use crate::target::{ - uarte0, - UARTE0, -}; +#[cfg(not(feature = "9160"))] +use crate::target::{uarte0, UARTE0}; -use crate::target_constants::EASY_DMA_SIZE; +use crate::gpio::{Floating, Input, Output, Pin, PushPull}; use crate::prelude::*; -use crate::gpio::{ - Pin, - Output, - PushPull, - Input, - Floating, -}; +use crate::target_constants::EASY_DMA_SIZE; use crate::timer::{self, Timer}; // Re-export SVD variants to allow user to directly set values -pub use uarte0::{ - baudrate::BAUDRATEW as Baudrate, - config::PARITYW as Parity, -}; - +pub use uarte0::{baudrate::BAUDRATEW as Baudrate, config::PARITYW as Parity}; /// Interface to a UARTE instance /// @@ -54,7 +37,10 @@ pub use uarte0::{ /// - nrf52840: Section 6.1.2 pub struct Uarte(T); -impl Uarte where T: Instance { +impl Uarte +where + T: Instance, +{ pub fn new(uarte: T, mut pins: Pins, parity: Parity, baudrate: Baudrate) -> Self { // Select pins uarte.psel.rxd.write(|w| { @@ -95,21 +81,16 @@ impl Uarte where T: Instance { }); // Enable UARTE instance - uarte.enable.write(|w| - w.enable().enabled() - ); + uarte.enable.write(|w| w.enable().enabled()); // Configure let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some(); - uarte.config.write(|w| - w.hwfc().bit(hardware_flow_control) - .parity().variant(parity) - ); + uarte + .config + .write(|w| w.hwfc().bit(hardware_flow_control).parity().variant(parity)); // Configure frequency - uarte.baudrate.write(|w| - w.baudrate().variant(baudrate) - ); + uarte.baudrate.write(|w| w.baudrate().variant(baudrate)); Uarte(uarte) } @@ -120,11 +101,7 @@ impl Uarte where T: Instance { /// /// The buffer must have a length of at most 255 bytes on the nRF52832 /// and at most 65535 bytes on the nRF52840. - pub fn write(&mut self, - tx_buffer : &[u8], - ) - -> Result<(), Error> - { + pub fn write(&mut self, tx_buffer: &[u8]) -> Result<(), Error> { if tx_buffer.len() > EASY_DMA_SIZE { return Err(Error::TxBufferTooLong); } @@ -151,8 +128,7 @@ impl Uarte where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(tx_buffer.as_ptr() as u32) } - ); + unsafe { w.ptr().bits(tx_buffer.as_ptr() as u32) }); self.0.txd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -202,11 +178,7 @@ impl Uarte where T: Instance { /// until the buffer is full. /// /// The buffer must have a length of at most 255 bytes - pub fn read(&mut self, - rx_buffer : &mut [u8], - ) - -> Result<(), Error> - { + pub fn read(&mut self, rx_buffer: &mut [u8]) -> Result<(), Error> { self.start_read(rx_buffer)?; // Wait for transmission to end @@ -239,8 +211,10 @@ impl Uarte where T: Instance { &mut self, rx_buffer: &mut [u8], timer: &mut Timer, - cycles: u32 - ) -> Result<(), Error> where I: timer::Instance + cycles: u32, + ) -> Result<(), Error> + where + I: timer::Instance, { // Start the read self.start_read(rx_buffer)?; @@ -303,8 +277,7 @@ impl Uarte where T: Instance { // // The PTR field is a full 32 bits wide and accepts the full range // of values. - unsafe { w.ptr().bits(rx_buffer.as_ptr() as u32) } - ); + unsafe { w.ptr().bits(rx_buffer.as_ptr() as u32) }); self.0.rxd.maxcnt.write(|w| // We're giving it the length of the buffer, so no danger of // accessing invalid memory. We have verified that the length of the @@ -336,8 +309,7 @@ impl Uarte where T: Instance { /// Stop an unfinished UART read transaction and flush FIFO to DMA buffer fn cancel_read(&mut self) { // Stop reception - self.0.tasks_stoprx.write(|w| - unsafe { w.bits(1) }); + self.0.tasks_stoprx.write(|w| unsafe { w.bits(1) }); // Wait for the reception to have stopped while self.0.events_rxto.read().bits() == 0 {} @@ -346,8 +318,7 @@ impl Uarte where T: Instance { self.0.events_rxto.write(|w| w); // Ask UART to flush FIFO to DMA buffer - self.0.tasks_flushrx.write(|w| - unsafe { w.bits(1) }); + self.0.tasks_flushrx.write(|w| unsafe { w.bits(1) }); // Wait for the flush to complete. while self.0.events_endrx.read().bits() == 0 {} @@ -361,7 +332,10 @@ impl Uarte where T: Instance { } } -impl fmt::Write for Uarte where T: Instance { +impl fmt::Write for Uarte +where + T: Instance, +{ fn write_str(&mut self, s: &str) -> fmt::Result { // Copy all data into an on-stack buffer so we never try to EasyDMA from // flash @@ -382,7 +356,6 @@ pub struct Pins { pub rts: Option>>, } - #[derive(Debug)] pub enum Error { TxBufferTooLong, @@ -393,10 +366,9 @@ pub enum Error { BufferNotInRAM, } - pub trait Instance: Deref {} impl Instance for UARTE0 {} -#[cfg(any(feature="52840", feature="9160"))] +#[cfg(any(feature = "52840", feature = "9160"))] impl Instance for UARTE1 {} diff --git a/nrf52810-hal/build.rs b/nrf52810-hal/build.rs index 2374a72e..88f7fef8 100644 --- a/nrf52810-hal/build.rs +++ b/nrf52810-hal/build.rs @@ -14,4 +14,4 @@ fn main() { println!("cargo:rerun-if-changed=build.rs"); println!("cargo:rerun-if-changed=memory.x"); -} \ No newline at end of file +} diff --git a/nrf52810-hal/src/lib.rs b/nrf52810-hal/src/lib.rs index 20da4b5a..8154e4ee 100644 --- a/nrf52810-hal/src/lib.rs +++ b/nrf52810-hal/src/lib.rs @@ -15,6 +15,6 @@ pub use crate::clocks::Clocks; pub use crate::delay::Delay; pub use crate::saadc::Saadc; pub use crate::spim::Spim; +pub use crate::temp::Temp; pub use crate::timer::Timer; pub use crate::uarte::Uarte; -pub use crate::temp::Temp; diff --git a/nrf52832-hal/build.rs b/nrf52832-hal/build.rs index f523a095..7ec0411f 100644 --- a/nrf52832-hal/build.rs +++ b/nrf52832-hal/build.rs @@ -7,16 +7,15 @@ fn main() { // Put the linker script somewhere the linker can find it let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - let linker = match (cfg!(feature = "xxAA-package"), cfg!(feature = "xxAB-package")) { + let linker = match ( + cfg!(feature = "xxAA-package"), + cfg!(feature = "xxAB-package"), + ) { (false, false) | (true, true) => { panic!("\n\nMust select exactly one package for linker script generation!\nChoices: 'xxAA-package' or 'xxAB-package'\n\n"); } - (true, false) => { - include_bytes!("memory_xxAA.x") - } - (false, true) => { - include_bytes!("memory_xxAB.x") - } + (true, false) => include_bytes!("memory_xxAA.x"), + (false, true) => include_bytes!("memory_xxAB.x"), }; File::create(out.join("memory.x")) diff --git a/nrf52840-hal/src/lib.rs b/nrf52840-hal/src/lib.rs index 88f19356..76c99393 100644 --- a/nrf52840-hal/src/lib.rs +++ b/nrf52840-hal/src/lib.rs @@ -15,6 +15,6 @@ pub use crate::clocks::Clocks; pub use crate::delay::Delay; pub use crate::saadc::Saadc; pub use crate::spim::Spim; +pub use crate::temp::Temp; pub use crate::timer::Timer; pub use crate::uarte::Uarte; -pub use crate::temp::Temp; diff --git a/nrf9160-hal/src/lib.rs b/nrf9160-hal/src/lib.rs index 8f840210..12a77b7f 100644 --- a/nrf9160-hal/src/lib.rs +++ b/nrf9160-hal/src/lib.rs @@ -1,8 +1,8 @@ #![no_std] use embedded_hal as hal; -pub use nrf9160_pac as pac; pub use nrf52_hal_common::*; +pub use nrf9160_pac as pac; pub mod prelude { pub use crate::hal::prelude::*; diff --git a/rustfmt.toml b/rustfmt.toml new file mode 100644 index 00000000..e69de29b diff --git a/scripts/build.sh b/scripts/build.sh index 0823507a..a2a1d94e 100755 --- a/scripts/build.sh +++ b/scripts/build.sh @@ -37,3 +37,5 @@ echo Building examples/twi-ssd1306... cargo build --manifest-path examples/twi-ssd1306/Cargo.toml echo Building examples/twi-ssd1306... cargo build --manifest-path examples/twi-ssd1306/Cargo.toml --no-default-features --features="52840" --target thumbv7em-none-eabi +echo Checking source code formatting... +cargo fmt -- --check