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applications: sdp: mspi: Add IPC solution to SDP MSPI application
Add IPC solution based on icmsg to application for FLPR core to communicate with SDP MSPI driver. Signed-off-by: Jakub Zymelka <[email protected]>
1 parent 7c543a6 commit 1ea43cd

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7 files changed

+222
-60
lines changed

7 files changed

+222
-60
lines changed

‎applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,58 @@
44
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
55
*/
66

7+
/ {
8+
soc {
9+
reserved-memory {
10+
#address-cells = <1>;
11+
#size-cells = <1>;
12+
13+
sram_tx: memory@2003c000 {
14+
reg = <0x2003c000 0x0800>;
15+
};
16+
17+
sram_rx: memory@2003c800 {
18+
reg = <0x2003c800 0x0800>;
19+
};
20+
};
21+
};
22+
23+
ipc {
24+
ipc0: ipc0 {
25+
compatible = "zephyr,ipc-icmsg";
26+
tx-region = <&sram_tx>;
27+
rx-region = <&sram_rx>;
28+
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
29+
mbox-names = "rx", "tx";
30+
status = "okay";
31+
};
32+
};
33+
};
34+
35+
&cpuflpr_rram {
36+
reg = <0x17a000 DT_SIZE_K(12)>;
37+
};
38+
39+
&cpuflpr_code_partition {
40+
reg = <0x0 DT_SIZE_K(12)>;
41+
};
42+
43+
&cpuflpr_sram {
44+
reg = <0x2003d000 DT_SIZE_K(12)>;
45+
ranges = <0x0 0x2003d000 0x3000>;
46+
};
47+
48+
&cpuflpr_vevif_rx {
49+
status = "okay";
50+
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
51+
nordic,tasks = <1>;
52+
nordic,tasks-mask = <0x00010000>;
53+
};
54+
55+
&cpuflpr_vevif_tx {
56+
status = "okay";
57+
};
58+
759
&gpio0 {
860
status = "disabled";
961
};

‎applications/sdp/mspi/prj.conf‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1 +1,3 @@
11
CONFIG_MBOX=y
2+
CONFIG_IPC_SERVICE=y
3+
CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

‎applications/sdp/mspi/sample.yaml‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,10 @@ common:
55
integration_platforms:
66
- nrf54l15dk/nrf54l15/cpuflpr
77
tests:
8-
applications.sdp.mspi.icmsg:
8+
applications.sdp.mspi:
99
build_only: true
1010
sysbuild: true
1111
platform_allow: nrf54l15dk/nrf54l15/cpuflpr
1212
tags: ci_build sysbuild mspi
13-
extra_configs:
14-
- CONFIG_IPC_SERVICE=y
15-
- CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
13+
required_snippets:
14+
- sdp-mspi

‎applications/sdp/mspi/src/hrt/hrt.c‎

Lines changed: 35 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@
66
#include "hrt.h"
77
#include <hal/nrf_vpr_csr_vio.h>
88
#include <hal/nrf_vpr_csr_vtim.h>
9-
10-
#define TOP 4
9+
#include <drivers/mspi/nrfe_mspi.h>
1110

1211
void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
1312
uint8_t word_size, bool ce_enable_state, bool hold_ce)
@@ -17,13 +16,15 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
1716
/* Configuration step */
1817
uint16_t dir = nrf_vpr_csr_vio_dir_get();
1918

20-
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(CS_PIN) |
21-
PIN_DIR_OUT_MASK(SCLK_PIN));
19+
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
20+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
21+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
2222

2323
uint16_t out = nrf_vpr_csr_vio_out_get();
2424

25-
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_HIGH_MASK(CS_PIN) |
26-
PIN_OUT_LOW_MASK(SCLK_PIN));
25+
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
26+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
27+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
2728

2829
nrf_vpr_csr_vio_mode_out_t out_mode = {
2930
.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
@@ -60,8 +61,9 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
6061

6162
/* Enable CS */
6263
out = nrf_vpr_csr_vio_out_get();
63-
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
64-
out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
64+
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
65+
out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
66+
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
6567
nrf_vpr_csr_vio_out_set(out);
6668

6769
/* Start counter */
@@ -83,9 +85,11 @@ void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t co
8385
/* Deselect slave */
8486
if (!hold_ce) {
8587
out = nrf_vpr_csr_vio_out_get();
86-
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
87-
out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
88-
out |= PIN_OUT_LOW_MASK(SCLK_PIN);
88+
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
89+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
90+
out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
91+
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
92+
out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
8993
nrf_vpr_csr_vio_out_set(out);
9094
}
9195

@@ -102,15 +106,21 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
102106
/* Configuration step */
103107
uint16_t dir = nrf_vpr_csr_vio_dir_get();
104108

105-
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(D1_PIN) |
106-
PIN_DIR_OUT_MASK(D2_PIN) | PIN_DIR_OUT_MASK(D3_PIN) |
107-
PIN_DIR_OUT_MASK(CS_PIN) | PIN_DIR_OUT_MASK(SCLK_PIN));
109+
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
110+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
111+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
112+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
113+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
114+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
108115

109116
uint16_t out = nrf_vpr_csr_vio_out_get();
110117

111-
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_LOW_MASK(D1_PIN) |
112-
PIN_OUT_LOW_MASK(D2_PIN) | PIN_OUT_LOW_MASK(D3_PIN) |
113-
PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_LOW_MASK(SCLK_PIN));
118+
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
119+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
120+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
121+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)) |
122+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
123+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
114124

115125
nrf_vpr_csr_vio_mode_out_t out_mode = {
116126
.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
@@ -147,8 +157,9 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
147157

148158
/* Enable CS */
149159
out = nrf_vpr_csr_vio_out_get();
150-
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
151-
out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
160+
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
161+
out |= ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
162+
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
152163
nrf_vpr_csr_vio_out_set(out);
153164

154165
/* Start counter */
@@ -170,9 +181,11 @@ void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t coun
170181
/* Deselect slave */
171182
if (!hold_ce) {
172183
out = nrf_vpr_csr_vio_out_get();
173-
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
174-
out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
175-
out |= PIN_OUT_LOW_MASK(SCLK_PIN);
184+
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
185+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
186+
out |= ce_enable_state ? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
187+
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
188+
out |= PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER));
176189
nrf_vpr_csr_vio_out_set(out);
177190
}
178191

‎applications/sdp/mspi/src/hrt/hrt.h‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,6 @@
1010
#include <stdint.h>
1111
#include <stdbool.h>
1212

13-
#define SCLK_PIN 0
14-
#define D0_PIN 1
15-
#define D1_PIN 2
16-
#define D2_PIN 3
17-
#define D3_PIN 4
18-
#define CS_PIN 5
19-
2013
/* Max word size. */
2114
#define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX
2215

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