boards: shields: wifi: Add nRF7002-EB II shields

Add board files to enable use of nRF7002-EB II shield with
nRF54L15, nRF54LM20 DK boards

Signed-off-by: Bansidhar Mangalwedhekar <[email protected]>

Author: bama-nordic

boards/shields/nrf7002eb2/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

@@ -20,24 +20,26 @@
 &pinctrl {
 	spi22_default: spi22_default {
 		group1 {
-			psels = <NRF_PSEL(SPIM_SCK,  1, 4)>,
-				<NRF_PSEL(SPIM_MISO, 1, 5)>,
+			psels = <NRF_PSEL(SPIM_SCK,  1, 11)>,
+				<NRF_PSEL(SPIM_MISO, 1, 7)>,
 				<NRF_PSEL(SPIM_MOSI, 1, 6)>;
+			bias-pull-down;
 		};
 	};
 
 	spi22_sleep: spi22_sleep {
 		group1 {
-			psels = <NRF_PSEL(SPIM_SCK,  1, 4)>,
-				<NRF_PSEL(SPIM_MISO, 1, 5)>,
+			psels = <NRF_PSEL(SPIM_SCK,  1, 11)>,
+				<NRF_PSEL(SPIM_MISO, 1, 7)>,
 				<NRF_PSEL(SPIM_MOSI, 1, 6)>;
+			bias-pull-down;
 			low-power-enable;
 		};
 	};
 };
 
 &spi22 {
-	cs-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+	cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 	pinctrl-0 = <&spi22_default>;
 	pinctrl-1 = <&spi22_sleep>;
 	pinctrl-names = "default", "sleep";

boards/shields/nrf7002eb2/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "../nrf7002eb2_gpio_pins_2.dtsi"
+
+/ {
+	chosen {
+		zephyr,wifi = &wlan0;
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,uart-mcumgr = &uart30;
+		zephyr,bt-mon-uart = &uart30;
+		zephyr,bt-c2h-uart = &uart30;
+	};
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&pinctrl {
+	spi22_default: spi22_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 3, 3)>,
+				<NRF_PSEL(SPIM_MISO, 3, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 3, 0)>;
+			bias-pull-down;
+		};
+	};
+
+	spi22_sleep: spi22_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 3, 3)>,
+				<NRF_PSEL(SPIM_MISO, 3, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 3, 0)>;
+			bias-pull-down;
+			low-power-enable;
+		};
+	};
+
+	uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 7)>;
+			bias-pull-up;
+		};
+	};
+
+	uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 6)>,
+				<NRF_PSEL(UART_RX, 0, 7)>;
+			low-power-enable;
+		};
+	};
+};
+
+&spi22 {
+	status = "okay";
+	cs-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi22_default>;
+	pinctrl-1 = <&spi22_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* uart20 has pin conflicts with EB-II shield hence disabling that
+ * and enabling uart30 as console port.
+ */
+&uart20 {
+	status = "disabled";
+};
+
+&uart30 {
+	status = "okay";
+};

boards/shields/nrf7002eb2/boards/nrf54lm20dk_nrf54lm20a_cpuapp.overlay

@@ -10,14 +10,14 @@
 		status = "disabled";
 		status0-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
 		req-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-		grant-gpios = <&gpio1 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
+		grant-gpios = <&gpio1 12 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
 	};
 };
 
 &nrf70 {
-	iovdd-ctrl-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
-	bucken-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-	host-irq-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+	iovdd-ctrl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	bucken-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	host-irq-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 };
 
 &gpio1 {

boards/shields/nrf7002eb2/nrf7002eb2_gpio_pins_1.dtsi

@@ -8,16 +8,16 @@
 	nrf_radio_coex: coex {
 		compatible = "nordic,nrf7002-coex";
 		status = "disabled";
-		status0-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
-		req-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-		grant-gpios = <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
+		status0-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+		req-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+		grant-gpios = <&gpio1 7 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>;
 	};
 };
 
 &nrf70 {
-	iovdd-ctrl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-	bucken-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
-	host-irq-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+	iovdd-ctrl-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	bucken-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	host-irq-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 };
 
 &gpio1 {