|
| 1 | +&pinctrl { |
| 2 | + sqspi_default: sqspi_default { |
| 3 | + group1 { |
| 4 | + psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>, |
| 5 | + <NRF_PSEL(SDP_MSPI_CS0, 2, 5)>, |
| 6 | + <NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>; |
| 7 | + nordic,drive-mode = <NRF_DRIVE_E0E1>; |
| 8 | + }; |
| 9 | + group2 { |
| 10 | + psels = <NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>, |
| 11 | + <NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>, |
| 12 | + <NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>; |
| 13 | + nordic,drive-mode = <NRF_DRIVE_E0E1>; |
| 14 | + bias-pull-up; |
| 15 | + }; |
| 16 | + }; |
| 17 | + |
| 18 | + sqspi_sleep: sqspi_sleep { |
| 19 | + group1 { |
| 20 | + low-power-enable; |
| 21 | + psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>, |
| 22 | + <NRF_PSEL(SDP_MSPI_CS0, 2, 5)>, |
| 23 | + <NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>, |
| 24 | + <NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>, |
| 25 | + <NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>, |
| 26 | + <NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>; |
| 27 | + }; |
| 28 | + }; |
| 29 | +}; |
| 30 | + |
| 31 | +&cpuflpr_vpr { |
| 32 | + pinctrl-0 = <&sqspi_default>; |
| 33 | + pinctrl-1 = <&sqspi_sleep>; |
| 34 | + pinctrl-names = "default", "sleep"; |
| 35 | + interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>; |
| 36 | + status = "okay"; |
| 37 | +}; |
| 38 | + |
| 39 | +/ { |
| 40 | + reserved-memory { |
| 41 | + #address-cells = <1>; |
| 42 | + #size-cells = <1>; |
| 43 | + ranges; |
| 44 | + |
| 45 | + softperipheral_ram: memory@2003c000 { |
| 46 | + reg = <0x2003c000 0x4000>; |
| 47 | + ranges = <0 0x2003c000 0x4000>; |
| 48 | + #address-cells = <1>; |
| 49 | + #size-cells = <1>; |
| 50 | + |
| 51 | + sqspi: sqspi@3c00 { |
| 52 | + compatible = "nordic,nrf-sqspi"; |
| 53 | + #address-cells = <1>; |
| 54 | + #size-cells = <0>; |
| 55 | + reg = <0x3c00 0x200>; |
| 56 | + status = "okay"; |
| 57 | + zephyr,pm-device-runtime-auto; |
| 58 | + }; |
| 59 | + }; |
| 60 | + }; |
| 61 | +}; |
| 62 | + |
| 63 | +/delete-node/ &mx25r64; |
| 64 | + |
| 65 | +&sqspi { |
| 66 | + mx25r64: mx25r6435f@0 { |
| 67 | + compatible = "mxicy,mx25r", "jedec,mspi-nor"; |
| 68 | + status = "okay"; |
| 69 | + reg = <0>; |
| 70 | + jedec-id = [c2 28 17]; |
| 71 | + quad-enable-requirements = "S1B6"; |
| 72 | + sfdp-bfp = [ |
| 73 | + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb |
| 74 | + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 |
| 75 | + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 |
| 76 | + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff |
| 77 | + ]; |
| 78 | + size = <67108864>; |
| 79 | + has-dpd; |
| 80 | + t-enter-dpd = <10000>; |
| 81 | + t-exit-dpd = <35000>; |
| 82 | + t-reset-pulse = <10000>; |
| 83 | + t-reset-recovery = <35000>; |
| 84 | + |
| 85 | + mspi-max-frequency = <DT_FREQ_M(8)>; |
| 86 | + mspi-io-mode = "MSPI_IO_MODE_QUAD_1_4_4"; |
| 87 | + mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; |
| 88 | + mspi-hardware-ce-num = <1>; |
| 89 | + mspi-cpp-mode = "MSPI_CPP_MODE_0"; |
| 90 | + mspi-endian = "MSPI_BIG_ENDIAN"; |
| 91 | + mspi-ce-polarity = "MSPI_CE_ACTIVE_LOW"; |
| 92 | + }; |
| 93 | +}; |
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