doc: mpsl: fem: align ensure DPPIC and PPIB instances enabled

The doc for nrf2220, nrf21540_gpio, nrf21540_gpio_spi is aligned
for nrf54l.

Signed-off-by: Andrzej Kuros <[email protected]>

Author: ankuns

doc/nrf/app_dev/device_guides/fem/fem_nrf21540_gpio.rst

@@ -89,4 +89,12 @@ To use nRF21540 in GPIO mode, complete the following steps:
    * ``tx-en-settle-time-us`` to the value ``27``.
    * ``rx-en-settle-time-us`` to the value ``12``.
 
-   Ensure the instances ``dppic10``, ``dppic20``, ``dppic30``, ``ppib11``, ``ppib21``, ``ppib22``, ``ppib30`` are enabled (have ``status = "okay";``) in the devicetree.
+   Ensure that the following devicetree instances are enabled (have ``status = "okay"``):
+
+   * ``dppic10``
+   * ``dppic20``
+   * ``dppic30``
+   * ``ppib11``
+   * ``ppib21``
+   * ``ppib22``
+   * ``ppib30``

doc/nrf/app_dev/device_guides/fem/fem_nrf21540_gpio_spi.rst

@@ -132,7 +132,15 @@ To use nRF21540 in GPIO+SPI mode, complete the following steps:
    * ``tx-en-settle-time-us`` to the value ``27``.
    * ``rx-en-settle-time-us`` to the value ``12``.
 
-   Ensure the instances ``dppic10``, ``dppic20``, ``dppic30``, ``ppib11``, ``ppib21``, ``ppib22``, ``ppib30`` are enabled (have ``status = "okay";``) in the devicetree.
+   Ensure that the following devicetree instances are enabled (have ``status = "okay"``):
+
+   * ``dppic10``
+   * ``dppic20``
+   * ``dppic30``
+   * ``ppib11``
+   * ``ppib21``
+   * ``ppib22``
+   * ``ppib30``
 
 .. note::
    The nRF21540 GPIO-only mode of operation is selected by default in Kconfig when an nRF21540 node is provided in devicetree, as mentioned in the :ref:`ug_radio_fem_sw_support` section.

doc/nrf/app_dev/device_guides/fem/fem_nrf2220.rst

@@ -125,34 +125,12 @@ To use nRF2220, complete the following steps:
    It is recommended to use the GPIO pins that belong to the PERI Power Domain of the nRF54L device.
    For example, on the nRF54L15, these are pins belonging to GPIO P1.
    Using pins belonging to Low Power Domain (GPIO P0 on nRF54L15) is supported but requires more DPPI and PPIB channels of the SoC.
-   Enable appropriate instances of the ``DPPIC`` and ``PPIB`` peripherals in the devicetree file:
-
-   .. code-block:: devicetree
-
-      &dppic10 {
-            status = "okay";
-      };
-
-      &ppib11 {
-            status = "okay";
-      };
-
-      &ppib21 {
-            status = "okay";
-      };
-
-      &dppic20 {
-            status = "okay";
-      };
-
-      &ppib22 {
-            status = "okay";
-      };
-
-      &ppib30 {
-            status = "okay";
-      };
-
-      &dppic30 {
-            status = "okay";
-      };
+   Ensure that the following devicetree instances are enabled (have ``status = "okay"``):
+
+   * ``dppic10``
+   * ``dppic20``
+   * ``dppic30``
+   * ``ppib11``
+   * ``ppib21``
+   * ``ppib22``
+   * ``ppib30``