snippets: sdp: mspi: Add SDP MSPI snippet files

Add new snippet files for SDP MSPI.

Signed-off-by: Jakub Zymelka <[email protected]>

Author: jaz1-nordic

snippets/sdp/mspi/app.conf

@@ -0,0 +1,4 @@
+CONFIG_MSPI=y
+CONFIG_MBOX=y
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

snippets/sdp/mspi/flpr.conf

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+CONFIG_MBOX=y
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

snippets/sdp/mspi/sdp-mspi-app.overlay

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+&cpuflpr_vpr {
+	status = "okay";
+
+	sdp_mspi: sdp_mspi {
+		compatible = "nordic,nrfe-mspi-controller";
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};

snippets/sdp/mspi/snippet.yml

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+name: sdp-mspi
+
+boards:
+  /.*/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: sdp-mspi-app.overlay
+      EXTRA_CONF_FILE: app.conf
+  /.*/cpuflpr/:
+    append:
+      EXTRA_CONF_FILE: flpr.conf
+  /.*/nrf54l15/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: soc/nrf54l15_cpuapp.overlay

snippets/sdp/mspi/soc/nrf54l15_cpuapp.overlay

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpuflpr_code_partition: image@17a000 {
+				reg = <0x17a000 DT_SIZE_K(12)>;
+			};
+
+			sram_rx: memory@2003c000 {
+				reg = <0x2003c000 0x0800>;
+			};
+
+			sram_tx: memory@2003c800 {
+				reg = <0x2003c800 0x0800>;
+			};
+		};
+
+
+		cpuflpr_sram_code_data: memory@2003d000 {
+			compatible = "mmio-sram";
+			reg = <0x2003d000 DT_SIZE_K(12)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x2003d000 0x3000>;
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 16>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1512)>;
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(244)>;
+	ranges = <0x0 0x20000000 0x3d000>;
+};
+
+&cpuflpr_vpr {
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
+
+&pinctrl {
+	/omit-if-no-ref/ sdp_mspi_default: sdp_mspi_default {
+		group1 {
+			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
+				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>,
+				<NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
+				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
+				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
+			nordic,drive-mode = <NRF_DRIVE_H0H1>;
+		};
+	};
+	/omit-if-no-ref/ sdp_mspi_sleep: sdp_mspi_sleep {
+		group1 {
+			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
+				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>,
+				<NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
+				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
+				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
+			low-power-enable;
+		};
+	};
+};
+
+&sdp_mspi {
+	clock-frequency = <DT_FREQ_M(48)>;
+	pinctrl-0 = <&sdp_mspi_default>;
+	pinctrl-1 = <&sdp_mspi_sleep>;
+	pinctrl-names = "default", "sleep";
+	ce-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};